Faculty Publications

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Subject: search.filters.subject.CMOS integrated circuits

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    Widely programmable high-frequency active RC filters in CMOS technology
    (Institute of Electrical and Electronics Engineers Inc., 2009) Laxminidhi, T.; Prasadu, V.; Pavan, S.
    We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of "constant capacitance scaling"is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 7times; range. The filter core, designed in a 0.18-?m CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB. © 2009 IEEE.
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    Low power continuous time common mode sensing for common mode feedback circuits
    (2010) Pramod, M.; Laxminidhi, T.
    Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 ?m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits. © World Scientific Publishing Company.
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    Visualization of coherent structures in turbulent subsonic jet using planar laser induced fluorescence of acetone
    (2013) Shelar, V.M.; Hegde, G.M.; Umesh, G.; Jagadeesh, G.; Reddy, K.P.J.
    In this paper, we present the molecular density distribution measurement in turbulent nitrogen jet (Re ? 3×103), using acetone as molecular tracer. The tracer was seeded in the nitrogen jet by purging through the liquid acetone at ambient temperature. Planar laser sheet of 266 nm wavelength from frequency quadrupled, Q-switched, Nd:YAG laser was used as an excitation source. Emitted fluorescence images of jet flow field were recorded on CMOS camera. The dependence of planar laser induced fluorescence (PLIF) intensity on acetone vapor density was used to convert PLIF image of nitrogen jet into the density image on pixel-by-pixel basis. Instantaneous quantitative density image of nitrogen jet, seeded with acetone, was obtained. The arrowhead-shaped coherent turbulent structures were observed in the present work. It was found that coherent structures were non-overlapping with separate boundaries. Breaking of coherent structures into turbulence was clearly observed above four times jet width. © EDP Sciences, 2013.
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    Low voltage, low power chebyshev filter in 0.18 ?m cmos technology
    (2013) Rekha, S.; Laxminidhi, T.
    This paper presents an active-RC continuous time filter in 0.18 ?m standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 ?W. © 2013 World Scientific Publishing Company.
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    Common mode feedback circuits for low voltage fully-differential amplifiers
    (World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.
    Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.
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    Reconfigurable highly efficient CMOS-based dual input variable output switched capacitor converter for low power applications
    (Institution of Engineering and Technology journals@theiet.org, 2018) Abraham, C.; Subburaj, V.; Jena, D.; Parthiban, P.; Jose, B.R.; Mathew, J.
    A reconfigurable switched capacitor converter (SCC) topology with nine/ten CMOS switches and two flying capacitors is presented. It is capable of accepting two input sources simultaneously with an input voltage in the range of 1-2.5 V and delivers the output for 15 conversion ratios. The proposed SCC can drive a load current ranging from 10 ?A to 10 mA at an open loop efficiency of >90%. One of the important applications of the proposed converter is the utilisation of photovoltaic (PV) or the combination of PV and other direct current sources. The regulation of the output voltage can be achieved either by changing the voltage conversion ratios or using variable switching frequency.
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    11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor
    (Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.
    In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.
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    14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
    (Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.
    In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.
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    An integrated cascode DE power amplifier for RF calibration system towards measurement of bio-sensor applications
    (John Wiley and Sons Inc. P.O.Box 18667 Newark NJ 07191-8667, 2019) Kumar, R.; Kumar Kanaujia, B.K.; Dwari, S.; Kumar, S.; Song, H.
    The integrated cascode DE power amplifier for RF calibration system toward measurement of bio-sensor applications is presented in this paper. The proposed architecture includes cascode class-D and class-E amplifier stages that could provide better calibration accuracy in terms of wide bandwidth, power efficiency, high gain, minimum group delay, and lowest calibration system. The achieved high performance of proposed amplifier overcomes conventional measurement issues toward bio-sensor application. The inductive ?-shape matching network drives RF input to class-D stage and provides wide bandwidth of operation. While class-E stage with T-shape matching network maintains stable gain and high efficiency in desired band of operation. The performance of the CMOS proposed amplifier is executed in RF ADS simulator along with fabricated chip using commercial TSMC 65 nm manufacturing process. The simulated and measured data achieves Ku band (12 GHz to 18 GHz) with almost flat gain of 30 dB. The DE amplifier provides an output and saturated power of 17 dBm with highest power efficiency of 45%. The measured calibration factor at maximum resonant frequency of 13.5 GHz achieves best value of less than 2 dB within input power range of ?50 dBm to 0 dBm. The lowest calibration factor provides best accuracy along with the other parameters and could be beneficial toward bio-sensor measurement in the various applications. The calculated area of the fabricated chip is as 0.45*0.45mm2 where class-E consuming area of 38% and class-D of 44%. The fabricated chip consumes less power consumption of 3.2 mW under power supply of 1 V. © 2018 Wiley Periodicals, Inc.
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    Investigation of CMOS Based Integration Approach Using DAI Technique for Next Generation Wireless Networks
    (Springer New York LLC barbara.b.bertram@gsk.com, 2019) Roy, G.M.; Kanuajia, B.K.; Dwari, S.; Kumar, S.; Song, H.
    This research work investigates a CMOS based low noise amplifier (LNA) using differential active inductor with eight-shaped patch antenna for next generation wireless communication. The proposed work conceded into three different phases. The first phase proposes LNA architecture which includes multistage cascode amplifier with a gate inductor gain peaking technique. The ground approach for this architecture employs active inductor technique that includes two stages of differential amplifier. The proposed novel technique leads to give incremental in inductance by using of common mode feedback resistor and lowers the undesirable parasitic resistance effect. Additionally, this technique offers gain enhanced noise cancellation and achieves a frequency band of around 5.7 GHz. The proposed architecture includes single stage differential AI and enhances the bandwidth up to 6.8 GHz with peak gain of 21 dB at 7.8 GHz. The noise figure and stability factor are achieved which is reasonably good at 1 dB. The proposed architecture is design and optimized on advanced design RF simulator using 0.045 µm CMOS process technology. While in second phase, a narrow band eight-shaped patch antenna is designed which provides operating band range from 5.8 to 6.5 GHz with 6.2 GHz resonating frequency. Highest peak gain of 15 dB and maximum radiation power of 42.5 dBm is succeed by proposed antenna. The final phase provides integration strategy of LNA with antenna and achieves desired gain of nearly 21 dB with minimum NF of 1.2–1.5 dB in the same band. © 2018, Springer Science+Business Media, LLC, part of Springer Nature.