Faculty Publications
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Publications by NITK Faculty
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Item On the improved performance of luby transform codes over selective repeat ARQ in turbulent free space optical links(2013) Prakash, G.; Nayak, A.; Kulkarni, M.; Acharya, S.Free Space Optical (FSO) links are capable of offering high data transfer rates, secure and low interference links for connectivity as a last mile solution. However, atmospheric turbulence can degrade the performance for distances over 1 km. This degradation is in the form of packet loss and hence drop in the error performance. Error Control Coding (ECC) can be used to mitigate the effects of the atmospheric turbulence. In this paper we prove analytically and verify through simulations that Luby Transform(LT) Codes show an improved performance over Automatic Repeat Request(ARQ) schemes for FSO transmission. FSO systems are limited by the safety limits of the input power to the laser transmitter. A notable contribution in this paper is that we prove that this improvement with LT codes is within Maximum Permissible Exposure (MPE) limit for an FSO link for a BER performance of 10-5. © 2013 IEEE.Item Predictive Selective Repeat - an Optimized Selective Repeat for Noisy Channels(Institute of Electrical and Electronics Engineers Inc., 2023) Rati Preethi, S.; Praveen Kumar, P.; Anil, S.; Chandavarkar, B.R.Automatic Repeat reQuest (ARQ) is a technique used in two-way communication systems to make sure that the transmitted data is received properly without any errors. The underlying mechanism on which ARQ operates is the acknowledgment (ACK) sent by the receiver to the sender on the orderly arrival of data frames. Some protocols which have been employed include Stop and Wait ARQ, Go-Back-N ARQ, and Selective Repeat ARQ. There have been many attempts to optimize these protocols to decrease the number of Round-Trips and increase the throughput. Predictive Selective Repeat (PSR) ARQ is the technique introduced in this paper to send multiple copies of frames without waiting for ACK. The main goal of PSR ARQ model is to optimally predict the number of required copies for a particular frame so as to reduce the number of Round-Trips by using a Time series Forecasting Long Short-Term Memory (LSTM) model. © 2023 IEEE.Item EFH - An Efficient Fault-Tolerant Routing Methodology for 2D Mesh NoCs(Institute of Electrical and Electronics Engineers Inc., 2025) Bhowmik, B.; Girish, K.K.; Raju, A.J.; Chakraborty, R.The increasing complexity of modern System-on-Chip (SoC) designs demands reliable and scalable communication frameworks. Network-on-Chip (NoC) architectures, particularly the 2D Mesh topology, have gained prominence due to their structured layout and scalability, facilitating efficient data routing among interconnected functional blocks. However, the 2D Mesh topology remains highly vulnerable to static and dynamic faults, which disrupt network performance and increase congestion. Existing fault-tolerant routing algorithms struggle with handling complex fault patterns, such as concave and irregular fault regions, leading to increased latency and packet loss. This paper introduces the Entrance, First, Hole (EFH) routing methodology, which employs a dynamic node-labeling strategy to classify nodes into entrance, first, and hole nodes. This classification enables the network to bypass faults, maintain functional nodes, and optimize routing paths without introducing significant overhead. Experimental results using the Noxim NoC simulator demonstrate that EFH significantly enhances network throughput, reduces latency, and improves overall fault resilience compared to existing approaches. © 2025 IEEE.Item CARED: Cautious Adaptive RED gateways for TCP/IP networks(2012) Tahiliani, M.P.; Shet, K.C.; Basavaraju, T.G.Random Early Detection (RED) is a widely deployed active queue management algorithm that improves the overall performance of the network in terms of throughput and delay. The effectiveness of RED algorithm, however, highly depends on appropriate setting of its parameters. Moreover, the performance of RED is quite sensitive to abrupt changes in the traffic load. In this paper, we propose a Cautious Adaptive Random Early Detection (CARED) algorithm that dynamically varies maximum drop probability based on the level of traffic load to improve the overall performance of the network. Based on extensive simulations conducted using Network Simulator-2 (ns-2), we show that CARED algorithm reduces the packet drop rate and achieves high throughput as compared to RED, Adaptive RED and Refined Adaptive RED. Unlike other RED based algorithms, CARED algorithm does not introduce new parameters to achieve performance gain and hence can be deployed without any additional complexity. © 2011 Elsevier Ltd. All rights reserved.Item Performance analysis of a cooperative MAC protocol of wireless ad hoc networks(Medknow Publications B9, Kanara Business Centre, off Link Road, Ghatkopar (E) Mumbai 400 075, 2014) Chavhan, S.; Venkataram, P.; Chetan Kumar, S.; Kamath, S.S.Different medium access control (MAC) layer protocols, for example, IEEE 802.11 series and others are used in wireless local area networks. They have limitation in handling bulk data transfer applications, like video-on-demand, videoconference, etc. To avoid this problem a cooperative MAC protocol environment has been introduced, which enables the MAC protocol of a node to use its nearby nodes MAC protocol as and when required. We have found on various occasions that specified cooperative MAC establishes cooperative transmissions to send the specified data to the destination. In this paper we propose cooperative MAC priority (CoopMACPri) protocol which exploits the advantages of priority value given by the upper layers for selection of different paths to nodes running heterogeneous applications in a wireless ad hoc network environment. The CoopMACPri protocol improves the system throughput and minimizes energy consumption. Using a Markov chain model, we developed a model to analyse the performance of CoopMACPri protocol; and also derived closed-form expression of saturated system throughput and energy consumption. Performance evaluations validate the accuracy of the theoretical analysis, and also show that the performance of CoopMACPri protocol varies with the number of nodes. We observed that the simulation results and analysis reflects the effectiveness of the proposed protocol as per the specifications. Copyright © 2014 by the IETE.Item A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding(Elsevier B.V., 2020) Girija Sravani, K.; Rao, R.This paper details a novel asynchronous pipelining methodology that maximizes the throughput buffering capacity and robustness of gate-level pipelined systems. The data paths in the proposed pipeline style are encoded using hybrid logic encoding scheme, which incorporates simplicity of the single-rail encoding and robustness of the dual-rail encoding. The control path that provides the synchronization between pipeline stages is constructed based on the simple and high-speed early acknowledgment protocol. Further, the proposed pipeline accommodates isolate phase to achieve 100% storage capacity. Two test cases: A 4-bit,10-stage FIFO and a 16-bit adder, have been designed in 90 nm technology to validate the proposed pipeline style. The FIFO has been laid out in the UMC 180 nm process using the cadence tool suite. The post-layout results of FIFO show 12.5% better throughput than the high capacity single-rail pipeline. Simulation results of the adder also reveal that the proposed structure achieves the throughput of 3.44 Giga-items/sec, which is 44.18% higher than the APCDP (Asynchronous pipeline based on constructed critical path) and 11.9% higher than the high capacity single-rail pipelines. © 2019 Elsevier B.V.Item Novel Asynchronous Pipeline Architectures for High-Throughput Applications(Springer, 2020) Girija Sravani, K.; Rao, R.This paper introduces two novel high-throughput asynchronous pipeline methods, suitable for gate-level pipelined systems. The proposed methods, named as early acknowledged hybrid (EA-Hybrid) and high-capacity hybrid pipeline with post-detection (PD-Hybrid), use hybrid data paths that can combine the robustness of dual-rail encoding and simplicity of single-rail encoding schemes. The domino logic style has been adopted for constructing the logic gates in each pipeline stage, as it can provide the latch-less feature. The control path of EA-Hybrid is built based on high-speed early acknowledgment protocol, whereas in PD-Hybrid, it is built based on simple and robust 4-phase protocol. Further, both the proposed pipeline styles allow their logic gates into a special state called the isolate phase in addition to precharge and evaluation phases. The isolate phase leads to improvement in pipeline throughput as well as storage capacity. An 8x8 array multiplier has been designed using the proposed pipeline styles and simulated in three different technologies using UMC libraries. In 180 nm technology, the proposed EA-Hybrid method has achieved 40.25% higher throughput and the pipeline style PD-Hybrid has achieved 18.05% higher throughput than the APCDP. © 2020, King Fahd University of Petroleum & Minerals.Item Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Girija Sravani, K.; Rao, R.This work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.