Faculty Publications
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Item Seamless transfer of microturbine generation system operation between grid-connected and islanding modes(2009) Gaonkar, D.N.; Pillai, G.N.; Patel, R.N.The intentional islanding operation of grid-connected distributed generation systems can greatly improve the reliability and quality of the power supply. The existing control techniques for distributed generation systems are designed to operate either in the grid-connected or islanding modes of operation, thus, not allowing for both modes to be implemented and transitioned between. In this article, a novel scheme for automatic mode switching of a microturbine-based distributed generation system between the grid-connected and islanding modes of operation is proposed. The presented scheme is based on the phase angle estimated by the phase-locked loop. The developed phase-locked loop provides an accurate estimation of the phase angle even under unbalanced conditions. The presented scheme does not negatively affect the distributed generation system or utility operations and can work even under matching distributed generation and load power ratings. In this work, back-to-back converters are used to interface the microturbine-based distributed generation system to the grid. Converter control strategies developed for both modes of distributed generation operation is also presented. The simulation results show good accuracy of the proposed scheme.Item Dual Role CDSC-Based Dual Vector Control for Effective Operation of DVR with Harmonic Mitigation(Institute of Electrical and Electronics Engineers Inc., 2019) Karthikeyan, A.; Abhilash Krishna, D.G.A.; Kumar, S.; Venkatesa Perumal, B.V.; Mishra, S.For the effective operation of a dynamic voltage restorer (DVR), a control strategy plays a significant role. This paper presents an enhanced control strategy for DVR using dual role cascaded delay signal cancellation (CDSC)-based dual vector control (DVC) under unbalanced and distorted grid conditions. Based on the numerical analysis, it is found that the CDSC prefilter is a promising solution when grid voltage is distorted by symmetric, asymmetric harmonics, and unbalanced sag. Mainly, the CDSC prefilter extracts instantaneous symmetrical components of the grid voltage required for voltage sags detection and generation of fundamental component of reference voltage for the DVR. A CDSC-based DVC algorithm with inductor current and capacitor voltage feedback is implemented in a synchronous reference frame, which tracks the fundamental DVR reference voltages. An extractor based on the modified CDSC strategy is designed to extract harmonics from load voltage during distorted grid conditions. These extracted harmonic components (nonfundamental) are added in phase opposition with fundamental component and fed to pulse width modulation block to generate reference voltages. Experimental studies are conducted on scaled down (100 V, 0.5 kVA) laboratory prototype DVR to verify the effectiveness of the proposed control algorithm under unbalanced and distorted grid conditions. © 1982-2012 IEEE.Item A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL(Birkhauser, 2020) Lad, H.; Rekha, S.; Laxminidhi, T.This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item Operation of the Microgrid with Improved Droop Control Strategy and an Effective Islanding Detection Technique for Automatic Mode Switching(Taylor and Francis Ltd., 2021) Kulkarni, S.V.; Gaonkar, D.N.; Guerrero, J.M.This paper presents the islanding detection and automatic mode switching for inverter-based distributed generation sources (DGs) in the microgrid with an improved droop controlled scheme. The modification in the conventional droop among the DGs is contrived to share the load proportionate to their power capacity. And to reduce the circulating currents and to improve reactive power-sharing the virtual impedance is implemented for the microgrid in the stand-alone mode operation. Also, the modified Park synchronous reference frame based phase-locked loop (PSRF-PLL) is implemented for the operation of the microgrid in the grid-connected mode. The islanding detection and automatic mode switching depend on the PSRF-PLL, which uses the input obtained from the stationary reference frame. The proposed PLL implemented in this work is simple in construction and keeps the phase locking error to near zero, thus leading to proper locking with reduced complexity. The control scheme's performance in the microgrid is validated using the real time hardware in the loop platform. The performance of PSRF-PLL based islanding detection scheme is analyzed considering the various grid disturbances, and the comparative study with the other PLL based scheme is also presented in this paper to show the improved performance of the proposed PSRF-PLL scheme. © 2021 Taylor & Francis Group, LLC.Item Low mismatch high-speed charge pump for high bandwidth phase locked loops(Elsevier Ltd, 2021) Lad Kirankumar, H.; Rekha, S.; Laxminidhi, T.This paper presents a low mismatch high-speed charge pump for high bandwidth phase locked loop (PLL). A novel mismatch compensation technique is used for reducing the current mismatch without having any extra area and power overhead. Proposed circuit is designed for 100 ?A charge pump current (ICP) and it achieves less than 1% mismatch current across all process corners for an output voltage compliance range of 0.2–1 V. A prototype circuit of 1 GHz PLL is designed in 65 nm CMOS technology for testing the proposed charge pump. It achieves ?81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 ?W power from 1.2 V supply including the reference current. Area occupied by proposed design is 72 × 35 ?m2. © 2021 Elsevier LtdItem HIL implementation of an islanding detection and an automatic mode switching for droop-based microgrid(Inderscience Publishers, 2022) Kulkarni, S.V.; Gaonkar, D.N.This paper presents the control schemes and performance study of parallel connected inverter based distributed generation sources (DGs) in microgrid for grid-connected and stand-alone modes of operation. This standalone mode of operation of inverter based DG system is mainly based on droop control scheme with the virtual complex impedance in the outer voltage loop. The microgrid load power is proportionally shared by the DGs according to their power ratings which features a good reliability and efficiency. Both the modes are switched automatically based on the Phase Locked Loop (PLL) phase error sin(γ – θ). This phase error is used to detect the islanding during disturbances in the system and also helps in seamless transfer between the modes. The PLL phase error response, islanding detection and mode switching are presented for various fault conditions. The hardware-in-the-loop (HIL) based platform is used to evaluate the performance of the microgrid in both the modes with islanding detection and automatic mode switching operation. © © 2022 Inderscience Enterprises Ltd.Item A Novel Islanding Detection Technique Based on Piezoelectric Sensors for Grid-Integrated DG Systems(Taylor and Francis Ltd., 2023) Kulkarni, S.V.; Hegde, V.; Gaonkar, D.N.This paper presents the novel islanding detection technique that depends on the piezoelectric sensors for distributed generation sources (DGs) in the grid-integrated operation mode. The islanding detection method employs a piezoelectric sensor for the detection of the frequency variations during grid disruptions. The designed diaphragm-based sensor has a natural frequency as that of the fundamental frequency of the system frequency signal. Any further deviations from the natural frequency due to the disturbances will be sensed by the sensor and a control signal is being sent to the associated circuit breaker for suitable action. The sensor structure is modeled using the finite element method and implemented in the Phase-Locked Loop (PLL) of the grid-integrated DGs. The proposed circular diaphragm-based sensor structure will have the bandwidth in the range of natural frequency with the tolerance rate of ±1% and uses the input signal received from the PLL controller outer loop. The proposed islanding detection technique’s performance and reliability for grid-integrated DG are validated using the real-time hardware in the loop test-bed platform. The HIL virtual simulated responses show that the method can be proposed effectively for islanding detection in the event of frequency variations in the grid-integrated DG systems. © 2023 IETE.Item Low Power, High Speed, Inductor-less Cascaded Charge Pump Phase Locked Loop(Birkhauser, 2025) Kirankumar, H.L.; Rekha, S.; Laxminidhi, T.A wide frequency range, inductor-less, charge pump phase locked loop (CP-PLL) is presented in this paper. It has a multi-phase, two stage cascaded architecture. This design uses a dead-zone free, zero blind-zone phase frequency detector (PFD) and a low mismatch charge pump (CP) circuit to generate low jitter clocks. A 3-stage single ended ring oscillator of 625 MHz VCO is designed for the first stage. An 8-phase feed-forward coupled VCO with programmable multi band ranging from 1.25 to 5 GHz is designed for the second stage of this cascaded system. Overall, this proposed cascaded PLL achieves jitter FOM and jitter-N FOM of -227.1 and ? 250.1 dB, respectively for 5 GHz output frequency with 1.44 ps rms jitter while consuming 9.24 mW of power from 1.2 V supply. This proposed clock generator circuit, designed in UMC 65 nm CMOS technology, occupies an area of 0.079 mm2. This study contributes to the development of energy-efficient, high speed clock generation solutions derived from a low reference clock. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.Item A Fast and Robust PLL Design with a Combination of Frequency-Adaptive Alpha-Beta-CDSC and SOGI(Institute of Electrical and Electronics Engineers Inc., 2025) Mondal, S.; Gayen, P.K.; Gaonkar, D.N.Recent research has focused on the enhancement of the prefiltering capability of phase-locked loops (PLL). The cascaded delayed signal cancellation (CDSC) PLL removes the low-order selective harmonic frequencies near the fundamental frequency. Here, a frequency-adaptive time delay unit is used to cope with frequency and phase variations of voltage. The high-frequency signal arising due to the frequency-adaptive loop cannot be mitigated. In effect, the transient response of adaptive CDSC-PLL shows a significant irregular pattern. Therefore, this article suggests the use of a second-order generalized integrator (SOGI) after the adaptive CDSC unit to improve the transient profile of frequency response. In the design, the high gain (K = 5.4) of SOGI is chosen to quickly settle the response of PLL at the expense of its ignorance of lower-order harmonics near the fundamental frequency. However, the lower-order harmonics are selectively eliminated by the CDSC unit. So, both prefilters complement each other's filtering capabilities. Additionally, the suggested prefilter provides improved noise immunity and eliminates DC offset via the SOGI unit. The linearized model and tuning procedure for the different control parameters of the proposed PLL are described. The real-time hardware-in-loop tests are executed to justify the optimum performance of the proposed PLL. © 2024 IEEE.