Faculty Publications
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Item A 1.2V 1.3μW Cascode Current Reuse Based Neural Amplifier with 113 dB Open-Loop Gain(Institute of Electrical and Electronics Engineers Inc., 2023) Korada, S.; Bhat, M.S.One of the major challenges in the acquisition of neural signals is the design of electronic signal acquisition system. Specialized amplifier circuitry is required in the neural recording system to accurately extract information from weak neural signals. High gain, high input impedance amplifiers are part of such systems. This paper presents the design of a high gain modified casocde current reuse open loop amplifier suitable for such applications. The amplifier has a open loop gain of 113 dB, a bandwidth of 10 kHz and unity-gain bandwidth (UGB) of 6.6 MHz. Further, design and simulation of high gain and low power neural amplifier is presented which uses the proposed high gain modified cascode current reuse amplifier with capacitive feedback. The neural amplifier has a closed loop gain of 45.8 dB over 85 Hz - 8.2 kHz and consumes approximately 1.3 μW of power. The design and the simulation is done using the UMC 90nm CMOS process employing 1.2 V power supply. The small signal DC gain, bandwidth and power of the neural amplifier are found to be better than the previously published works. © 2023 IEEE.Item Low power continuous time common mode sensing for common mode feedback circuits(2010) Pramod, M.; Laxminidhi, T.Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 ?m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits. © World Scientific Publishing Company.Item Common mode feedback circuits for low voltage fully-differential amplifiers(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits(Taylor and Francis Ltd, 2019) Kaliyath, Y.; Laxminidhi, T.This paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current ((Formula presented.)) of 4.79 µA, resulting in a power consumption of 8.62 µW. © 2019, © 2019 IETE.Item A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier LtdItem An area-efficient, large time-constant log-domain filter for low-frequency applications(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Hanumantha Rao, G.; Rekha, S.This paper proposes a simple technique to increase the time constant of a log-domain filter. By using the proposed technique, the capacitor value can be reduced considerably; hence, overall area of the circuit can be reduced. A second-order log-domain low-pass filter (LPF) is implemented in UMC 65-nm complementary metal-oxide semiconductor (CMOS) technology to validate the proposed technique. It occupies an area as low as 0.005 mm2 and operates with a 0.5-V supply. For a cutoff frequency of 100 Hz, the filter consumes a power of 4 nW. By adjusting the bias current, the cutoff frequency can be linearly tuned from 10 to 500 Hz. The filter has the figure of merit (FoM) of 0.68×10?13 J, which is on par with many designs listed in the literature. The filter uses the lowest capacitance/pole (0.92 pF) among the similar designs given in the literature, which shows that the present design is area efficient. © 2019 John Wiley & Sons, Ltd.Item Time Constant Enhancement Technique for Low-Frequency Filters(Birkhauser, 2020) Rao, G.H.; Rekha, S.This paper presents a simple and novel technique to enhance the time constant of a source follower (SF)-based low-pass filter (LPF) for front-end processing of biomedical signals. The proposed technique reduces the capacitor value significantly, which in turn reduces the area of the circuit. Inherent negative feedback and lower number of transistors in this circuit result in good linearity and dynamic range even with low power supply of 0.8 V. A second-order LPF of cutoff frequency (f-3dB) of 100 Hz is designed by cascading the proposed NMOS and PMOS SF LPFs. Cutoff frequency can be tuned linearly from 10 Hz to 1 kHz by varying the bias current and, hence, can be fit into the desired frequency range of different bio-potentials. The filter, designed in UMC 65 nm process, occupies an area of 0.008mm2. It offers a dynamic range of 61.85 dB while consuming a power as low as 8 nW. Figure of merit of the filter is as low as 3.23?10-14J which is better than many other filter designs reported in the literature. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.Item A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL(Birkhauser, 2020) Lad, H.; Rekha, S.; Laxminidhi, T.This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item A 0.8-V, 55.1-dB DR, 100 Hz Low-Pass Filter with Low-Power PTAT for Bio-Medical Applications(Taylor and Francis Ltd., 2022) Hanumantha Rao, G.; Rekha, S.This paper presents a power efficient transconductor-capacitor ((Formula presented.)) filter for front-end processing of bio-medical signals. A low voltage, low-power transconductor with improved output resistance is proposed. It offers a transconductance ((Formula presented.)) of 5.85 nS while operating at a supply voltage ((Formula presented.)) of 0.8 V. Furthermore, a low-power Proportional to Absolute Temperature (PTAT) current reference circuit is designed to bias the transconductor and to make (Formula presented.) independent of temperature. It follows PTAT characteristics in the temperature range of ?20 (Formula presented.) C to 70 (Formula presented.) C and is less sensitive to (Formula presented.) variations. A second-order Butterworth low-pass filter (LPF) with a cutoff frequency of 100 Hz is implemented to validate the proposed transconductor and the PTAT circuit. The filter is designed in UMC 65 nm CMOS process and it takes an area of 0.065 mm (Formula presented.). While consuming a power of 47 nW, it offers a dynamic range (DR) of 55.1 dB. Figure-of-merit (FoM) of the filter is as low as (Formula presented.) J, which is found to be on par with the filters reported in the literature. © 2022 IETE.