Faculty Publications
Permanent URI for this communityhttps://idr.nitk.ac.in/handle/123456789/18736
Publications by NITK Faculty
Browse
3 results
Search Results
Item A Support Vector Regression-Based Approach to Predict the Performance of 2D 3D On-Chip Communication Architectures(Institute of Electrical and Electronics Engineers Inc., 2019) Nirmal Kumar, A.; Talawar, B.Recently, Networks-on-Chips (NoCs) have evolved as a scalable solution to traditional bus and point-to-point architecture. NoC design performance evaluation is largely based on simulation, which is extremely slow as the architecture size increases, and it gives little insight on how distinct design parameters impact the actual performance of the network. Simulation for optimization purposes is therefore very difficult to use. In this paper, we propose a Support Vector Regression(SVR)-based framework, which can be used to analyze the performance of 2D and 3D NoC architectures. Experiments were conducted by varying architecture sizes with different virtual channels, injection rates. The framework proposed can be used to obtain fast and accurate NoC performance estimates with a prediction error 2% to 4% and minimum speedup of 3000 × to 3500×. © 2019 IEEE.Item LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures(World Scientific, 2022) Kumar, A.; Talawar, B.Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from 2×2 to 45×45 are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is 5000× to 5500× with respect to BookSim simulator. © 2022 World Scientific Publishing Company.Item A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment(Institute of Electrical and Electronics Engineers Inc., 2024) Kallinatha, H.D.; Rai, S.; Talawar, B.As the current primary memory technology is reaching its limits, it is essential to explore alternative memory technologies to accommodate modern applications and use cases. However, using new memory technology poses the challenge of deriving accurately estimated parameters for integrating new memory technology and doing reliable simulations. This study proposes a new approach incorporating Spin-Orbit-Torque-Magnetic-RAM (SOT-MRAM) into hybrid and full main memory architectures within a multi-core system, encompassing various memory configurations and capacities. The study addresses the challenge of evaluating SOT-MRAM-based memory systems when specific SOT-MRAM memory parameters are not publicly available. The research methodology includes micro-architectural (circuit-level) design space exploration and comprehensive full system simulations, which evaluate benchmark programs representing diverse application domains. The evaluation includes three memory structures with varying memory organizations and capacities. The results show that SOT-MRAM is a robust replacement for DRAM or hybrid memory, offering compelling advantages such as a remarkable 74.05% reduction in power consumption, a noteworthy 40.10% increase in bandwidth utilization, and a significant 72.85% reduction in Energy-Delay Product (EDP). The maximum latency penalties are also minimal, with a 3.71% increase for hybrid structures and a mere 0.07% for standalone SOT-MRAM memory structures. © 2013 IEEE.