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Item High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices(2012) Kumar, H.; Sripati, U.; Rajesh Shetty, K.In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application. © 2012 Taylor & Francis.Item Performance analysis of stack decoding on block coded modulation schemes using tree diagram(2012) Prashantha, K.H.; Vineeth, U.K.; Sripati, U.; Rajesh, Sh.K.The channel encoder adds redundancy in a structured way to provide error control capability. Modulator converts the symbol sequences from the channel encoder into waveforms which are then transmitted over the channel. Usually channel coder and modulator are implemented independently one after the other. But in a band limited channel better coding gains without sacrificing signal power are achieved when coding is combined with modulation. Block Coded Modulation (BCM) is such a scheme that results from the combination of linear block codes and modulation. In this paper we are proposing a stack decoding of rate 2/3 and rate 1/2 BCM schemes using tree structure and performance is compared with the Viterbi decoding that uses trellis representation. Simulation result shows that at reasonable bit error rate stack decoder performance is just 0.2 to 0.5 dB inferior to that of Viterbi decoding. Since stack decoding is a near optimum decoding scheme and whose decoding procedure is adaptable to noise level, we can consider this method in place of Viterbi decoding which is optimum and its decoding complexity grows exponentially with large code lengths. © K.H. Prashantha, U.K. Vineeth, U. Sripati, Sh.K. Rajesh, 2012.