Faculty Publications

Now showing 1 - 4 of 4

Design of Asynchronous Circular FIFO Buffer for Asynchronous Network on Chips
(Institute of Electrical and Electronics Engineers Inc., 2022) Chaturvedi, S.; Saranya, M.N.; Rao, R.
Network on Chip is employed for on-chip communication in multicore System-on-Chips for its advantages over bus-based architectures, more so with reducing feature size. The NoC implementation can be synchronous, asynchronous or Globally Asynchronous Locally Synchronous (GALS). However, synchronous design performance is limited by the global clock rate and depends on the slowest critical path, making it indispensable to optimize all portions of the design. Asynchronous design avoids clock skew and clock distribution issues on the chip and allows flexibility in the optimization of the rarely used portions of the system. Along with the benefit of reduced power consumption, they perform better in terms of delays, yielding average-case performance, as opposed to the worst-case performance yielded by the synchronous counterpart. One of the integral parts of NoC routers is buffers. In this paper, an asynchronous four-stage FIFO buffer based on domino logic and a synchronous four-stage FIFO buffer for comparison have been simulated using LTSpice on the TSMC 180nm technology. Results show that the proposed asynchronous design consumes 50% lesser power than the synchronous design, while maintaining a comparable performance in terms of latency and throughput. Â© 2022 IEEE.
Gain Enhanced Single-Stage Split Folded Cascode Operational Transconductance Amplifier
(Springer Science and Business Media Deutschland GmbH, 2023) Saranya, M.N.; Sriadibhatla, S.; Nagulapalli, R.
At the design level, meeting the performance requirement of applications demanding high gain operational transconductance amplifier (OTA) at low voltage in fine-line CMOS process technologies is a challenging task. This paper presents a split input differential pair design approach to enhance the DC gain of a standard folded cascode operational transconductance amplifier (SFCOTA). A Prototype implemented in TSMC 65Â nm CMOS technology demonstrates a significant performance enhancement without additional bias circuitry and voltage headroom penalty. The transistor-level preliminary simulation in Cadence Specter shows that the proposed amplifier achieves a better DC gain of 66.2Â dB and 261.5Â MHz unity-gain bandwidth, outperforming existing amplifier architectures. The circuit consumes 144.8Â ÂµW with a 1Â V supply making it suitable for low-voltage applications. Â© 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
A Comparative Analysis of Asynchronous and Synchronous NoC for Dynamic Traffic Handling using trace-inspired Synthetic Multimedia Data
(Institute of Electrical and Electronics Engineers Inc., 2024) Saranya, M.N.; Avinash, C.T.; Rao, R.
The paper investigates the feasibility of asynchronous Network-on-Chip (NoC) with wormhole switching in supporting traffic with variable data rates. A new approach to generate synthetic traffic close to realistic multimedia data traffic is also presented for the first time. This multimedia data stream traffic is utilized to evaluate the dynamic traffic handling capability of a generic synchronous NoC switch and asynchronous NoC switch architectures. Multimedia data streams are characterized as variable bit rate data streams where the amount of data being transmitted changes dynamically, depicting the heterogeneous timing of modern System-onChip (SoC). The Cadence Spectre Analog/Mixed Signal (AMS) Designer tool is used as a verification platform for the ease of simulation and to draw a fair comparison between the two architectures. The simulation platform is augmented with a real-time multimedia data stream for analysis. The simulation results show that the asynchronous design, activated only upon receiving data, outperforms the clock-triggered synchronous design in variable data-driven scenarios. Â© 2024 IEEE.
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems
(Springer, 2024) Saranya, M.N.; Rao, R.
The increasing multi-core system complexity with technology scaling introduces new constraints and challenges to interconnection network design. Consequently, the research community has a converging trend toward an asynchronous design paradigm for Network-on-Chip (NoC) architecture as a promising solution to these challenges. This paper addresses the design and functional verification aspects of an asynchronous NoC router microarchitecture for a Globally Asynchronous Locally Synchronous (GALS) system. Firstly, the paper introduces a novel mixed-level abstract simulation approach for faster functional verification of the asynchronous architecture using the commercially available Spectre Analog and mixed-signal simulation (AMS) Designer tool. This simulation methodology intends to ensure the feasibility of the design and identify shortcomings, if any, before the subsequent implementation stages of the design. Also, the paper proposes a new baseline asynchronous router built on a domino logic pipeline template with a novel hybrid encoding scheme. The new hybrid encoding scheme facilitates simple architecture with no additional timing constraints. The proposed verification methodology evaluates the baseline asynchronous router’s functional verification in Cadence’s AMS designer tool. Preliminary simulation results conform to the objectives of the paper. Further, the same verification setup establishes the design validation in subsequent stages of the design implementation. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.

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