Faculty Publications
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Publications by NITK Faculty
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Item Common mode feedback circuits for low voltage fully-differential amplifiers(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.Item A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier LtdItem An area-efficient, large time-constant log-domain filter for low-frequency applications(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Hanumantha Rao, G.; Rekha, S.This paper proposes a simple technique to increase the time constant of a log-domain filter. By using the proposed technique, the capacitor value can be reduced considerably; hence, overall area of the circuit can be reduced. A second-order log-domain low-pass filter (LPF) is implemented in UMC 65-nm complementary metal-oxide semiconductor (CMOS) technology to validate the proposed technique. It occupies an area as low as 0.005 mm2 and operates with a 0.5-V supply. For a cutoff frequency of 100 Hz, the filter consumes a power of 4 nW. By adjusting the bias current, the cutoff frequency can be linearly tuned from 10 to 500 Hz. The filter has the figure of merit (FoM) of 0.68×10?13 J, which is on par with many designs listed in the literature. The filter uses the lowest capacitance/pole (0.92 pF) among the similar designs given in the literature, which shows that the present design is area efficient. © 2019 John Wiley & Sons, Ltd.Item Time Constant Enhancement Technique for Low-Frequency Filters(Birkhauser, 2020) Rao, G.H.; Rekha, S.This paper presents a simple and novel technique to enhance the time constant of a source follower (SF)-based low-pass filter (LPF) for front-end processing of biomedical signals. The proposed technique reduces the capacitor value significantly, which in turn reduces the area of the circuit. Inherent negative feedback and lower number of transistors in this circuit result in good linearity and dynamic range even with low power supply of 0.8 V. A second-order LPF of cutoff frequency (f-3dB) of 100 Hz is designed by cascading the proposed NMOS and PMOS SF LPFs. Cutoff frequency can be tuned linearly from 10 Hz to 1 kHz by varying the bias current and, hence, can be fit into the desired frequency range of different bio-potentials. The filter, designed in UMC 65 nm process, occupies an area of 0.008mm2. It offers a dynamic range of 61.85 dB while consuming a power as low as 8 nW. Figure of merit of the filter is as low as 3.23?10-14J which is better than many other filter designs reported in the literature. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.Item A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL(Birkhauser, 2020) Lad, H.; Rekha, S.; Laxminidhi, T.This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item A 0.8-V, 55.1-dB DR, 100 Hz Low-Pass Filter with Low-Power PTAT for Bio-Medical Applications(Taylor and Francis Ltd., 2022) Hanumantha Rao, G.; Rekha, S.This paper presents a power efficient transconductor-capacitor ((Formula presented.)) filter for front-end processing of bio-medical signals. A low voltage, low-power transconductor with improved output resistance is proposed. It offers a transconductance ((Formula presented.)) of 5.85 nS while operating at a supply voltage ((Formula presented.)) of 0.8 V. Furthermore, a low-power Proportional to Absolute Temperature (PTAT) current reference circuit is designed to bias the transconductor and to make (Formula presented.) independent of temperature. It follows PTAT characteristics in the temperature range of ?20 (Formula presented.) C to 70 (Formula presented.) C and is less sensitive to (Formula presented.) variations. A second-order Butterworth low-pass filter (LPF) with a cutoff frequency of 100 Hz is implemented to validate the proposed transconductor and the PTAT circuit. The filter is designed in UMC 65 nm CMOS process and it takes an area of 0.065 mm (Formula presented.). While consuming a power of 47 nW, it offers a dynamic range (DR) of 55.1 dB. Figure-of-merit (FoM) of the filter is as low as (Formula presented.) J, which is found to be on par with the filters reported in the literature. © 2022 IETE.Item 1 V, 20 nW True RMS to DC Converter based on Third Order Dynamic Translinear Loop(Taylor and Francis Ltd., 2023) Mansoor, C.B.; Patii, A.; Rekha, S.This paper presents a novel current-mode true RMS–DC converter based on the dynamic translinear principle. The converter is designed using a third-order translinear loop, resulting in a very compact and simple circuit. The proposed circuit is designed in 65 nm CMOS technology, operates with 1 V power supply, has only 14 transistors and performs satisfactorily over a wide input current range of 300 nA–950 nA and for a frequency range of 600 Hz–650 kHz for a capacitance value of 10 nF. The frequency range of operation can be tuned by varying the external off chip capacitor and the bias current. The circuit consumes 20 nW static power, 1.6 μW maximum dynamic power and offers the lowest FOM among the other RMS–DC converter circuits presented in the literature. Comprehensive mathematical analysis along with the post layout simulation results confirm the validity of the proposed circuit. To test the use of converter in real world scenarios, the proposed converter is introduced within a typical ECG detection system and the results show that the circuit is an attractive solution for RMS–DC conversion in low-voltage low-power applications. © 2023 IETE.Item Low Power, High Speed, Inductor-less Cascaded Charge Pump Phase Locked Loop(Birkhauser, 2025) Kirankumar, H.L.; Rekha, S.; Laxminidhi, T.A wide frequency range, inductor-less, charge pump phase locked loop (CP-PLL) is presented in this paper. It has a multi-phase, two stage cascaded architecture. This design uses a dead-zone free, zero blind-zone phase frequency detector (PFD) and a low mismatch charge pump (CP) circuit to generate low jitter clocks. A 3-stage single ended ring oscillator of 625 MHz VCO is designed for the first stage. An 8-phase feed-forward coupled VCO with programmable multi band ranging from 1.25 to 5 GHz is designed for the second stage of this cascaded system. Overall, this proposed cascaded PLL achieves jitter FOM and jitter-N FOM of -227.1 and ? 250.1 dB, respectively for 5 GHz output frequency with 1.44 ps rms jitter while consuming 9.24 mW of power from 1.2 V supply. This proposed clock generator circuit, designed in UMC 65 nm CMOS technology, occupies an area of 0.079 mm2. This study contributes to the development of energy-efficient, high speed clock generation solutions derived from a low reference clock. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.Item A 0.6-V, 61-dB DR Fourth-Order Low-Pass Filter Using Folded Single-Branch Biquads(John Wiley and Sons Ltd, 2025) Muhammed Mansoor C, B.; Rekha, S.This paper proposes a novel, compact, and energy-efficient biquad which is derived from a folded single-branch transistorized (Formula presented.) -C structure. The biquad has a small number of active devices stacked between (Formula presented.) and GND rails and hence can be used satisfactorily in a low-voltage environment. The filter also inherits the benefits of folding in the circuit which makes the tuning of the filter easier and power independent. A fourth-order low-pass filter is used as a vehicle to illustrate the performance of the proposed biquad. The fully differential version of the filter is designed in 65-nm CMOS technology, operates with a supply voltage of 0.6 V, is biased with a current of 100 nA, has a (Formula presented.) 3-dB bandwidth of 15 kHz, and shows a dynamic range as high as 61 dB. The postlayout simulations along with FOM numbers show the superior performance of the filter. © 2025 John Wiley & Sons Ltd.