Faculty Publications
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Item Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). © 2024 IETE.Item Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer(Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1 to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET. © 2024 IETE.Item An improved Fourier series-based analytical model for threshold voltage and sub-threshold swing in SOI junctionless FinFET(Elsevier Ltd, 2024) Mathew, S.; Chennamadhavuni, S.; Rao, R.In this work, Fourier series-based analytical models for threshold voltage (Vth) and Sub-threshold Swing (SS) are developed for Junctionless Fin Field Effect Transistor (JLFinFET) on Silicon On Insulator (SOI) substrate, taking into account the location of the onset of current conduction in the channel. Rigorous simulations were conducted to analyse the current conduction path when JLFinFET surpasses the threshold voltage. Based on the findings from these simulations, threshold voltage condition used for deriving the threshold voltage model is modified. This modified model gives a better prediction of Vth for JLFinFET than the already existing model which doesn't include approximations based on the location of onset of current conduction. The analytical model developed for SS is also capable of closely predicting the SS of JLFinFET obtained from the TCAD simulator down to a gate length of 20 nm. © 2024 Elsevier LtdItem Fourier Series-Based Analytical Model for Channel Potential of Dual Material Gate SOI Junctionless FinFET(Springer, 2025) Mathew, S.; Rao, R.In this article, a robust Fourier series based analytical model for channel potential is derived for a Dual Material Gate Junctionless Fin Field Effect Transistor (DMG JLFinFET) on a Silicon-On-Insulator (SOI) substrate. For most of the regions in the cuboidal channel, especially at the location where the onset of current conduction happens, the channel potential model developed in this work matches very well with the potential obtained from TCAD simulations. The analytical model presented in this article is capable of calculating the channel potential of the DMG JLFinFETs for most of the channel region, considering various device parameters such as channel length, fin height, and fin width, with a maximum deviation of 0.07 V. However, for channel regions very close to buried oxide, the channel potential model over-predicts potential obtained through simulation by around 0.1 V. In most of the cases of varying device parameters, the Fourier series-based potential model developed in this work accurately predicts channel potential at the location of the onset of current conduction. Hence, it can be used to model various device parameters such as threshold voltage and sub-threshold swing. © The Minerals, Metals & Materials Society 2025.Item Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application(Institute of Physics, 2025) Vinaya, S.J.; Rao, R.; Nikhil, K.S.In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical characteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit.These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.