Faculty Publications

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    Heat treatment of friction surfaced steel-aluminum couple
    (Trans Tech Publications Ltd ttp@transtec.ch, 2015) Bhat, K.; Nithin; Bhat, S.; Sudeendran
    Friction surfacing is a solid state process and it is amenable for deposition of aluminum on steel. In this investigation, the mild steel surface was coated with a layer of aluminum using friction surfacing route. The aluminum thickness was in the range of 40-50 μm. It was followed by a heat treatment step to convert aluminum layer in to an aluminide layer. Heat treatment was done in open atmosphere at 700 °C for 2 hours. Microstuctural analysis showed that the aluminide layer is mainly made of Fe2Al5 and Fe4Al13, FeAl and Fe3Al are minor in fraction. Formation of Fe2Al5 is discussed. The aluminide layer also has some amount of porosities. © (2015) Trans Tech Publications, Switzerland.
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    Investigations on the effect of Dual Material Gate work function on DIBL and Subthreshold Swing in Junctionless FinFETs
    (Institute of Electrical and Electronics Engineers Inc., 2020) Mathew, S.; Nithin; Bhat, K.N.; Rao, R.
    This paper investigates the influence of gate material work function on the electrical characteristics as well as short channel effects exhibited by Dual Material Gate-Junctionless FinFETs (DMG-JLFinFETs) with channel length as low as 10 nm. 3D TCAD simulations performed on these devices show that various device parameters like threshold voltage, ON-current, etc, are influenced by the work function difference between the control gate and screen gate material of DMG-JLFinFET. DMG-JLFinFETs exhibit very low Drain Induced Barrier Lowering (DIBL), far lesser than its Single Material Gate (SMG) counterpart. Subthreshold Swing (SS) of DMG devices is higher than SMG devices. The optimal ratio of control gate length to total gate length in DMG-JLFinFET is found to be between 0.5 and 1 for better suppression of short channel effects. © 2020 IEEE.
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    Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode
    (Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.
    This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (Vth) and tunnelling current (Itunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. Itunn is lower when the work function of M1 (ΦM1) is greater than the work function of M2 (ΦM2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having ΦM1 < ΦM2. For devices with ΦM1 > ΦM2, SS can be improved by making a length of M1 (LM1) greater than 70% of the total gate length (Lg). © 2024 IETE.
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    Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer
    (Taylor and Francis Ltd., 2024) Mathew, S.; Bhat, K.N.; Nithin; Rao, R.
    In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (LSP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (ION), OFF current (IOFF), ratio of ION to IOFF (ION/IOFF), and tunneling current (Itunn), are closely monitored at gate lengths (Lg) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when Lg scales down from 30 nm to 10 nm. Except for the case of Itunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when LSP is 5 nm. Enhancement in analog performance metrics is observed when high κ materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V−1 to 47.4 V−1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high κ dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET. © 2024 IETE.