Faculty Publications
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Item Low power continuous time common mode sensing for common mode feedback circuits(2010) Pramod, M.; Laxminidhi, T.Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 ?m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits. © World Scientific Publishing Company.Item Common mode feedback circuits for low voltage fully-differential amplifiers(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits(Taylor and Francis Ltd, 2019) Kaliyath, Y.; Laxminidhi, T.This paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current ((Formula presented.)) of 4.79 µA, resulting in a power consumption of 8.62 µW. © 2019, © 2019 IETE.Item A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL(Birkhauser, 2020) Lad, H.; Rekha, S.; Laxminidhi, T.This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item Low Power, High Speed, Inductor-less Cascaded Charge Pump Phase Locked Loop(Birkhauser, 2025) Kirankumar, H.L.; Rekha, S.; Laxminidhi, T.A wide frequency range, inductor-less, charge pump phase locked loop (CP-PLL) is presented in this paper. It has a multi-phase, two stage cascaded architecture. This design uses a dead-zone free, zero blind-zone phase frequency detector (PFD) and a low mismatch charge pump (CP) circuit to generate low jitter clocks. A 3-stage single ended ring oscillator of 625 MHz VCO is designed for the first stage. An 8-phase feed-forward coupled VCO with programmable multi band ranging from 1.25 to 5 GHz is designed for the second stage of this cascaded system. Overall, this proposed cascaded PLL achieves jitter FOM and jitter-N FOM of -227.1 and ? 250.1 dB, respectively for 5 GHz output frequency with 1.44 ps rms jitter while consuming 9.24 mW of power from 1.2 V supply. This proposed clock generator circuit, designed in UMC 65 nm CMOS technology, occupies an area of 0.079 mm2. This study contributes to the development of energy-efficient, high speed clock generation solutions derived from a low reference clock. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.