Faculty Publications

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Publications by NITK Faculty

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Author: search.filters.author.Bhat, M.S.Subject: search.filters.subject.CMOS integrated circuits

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    11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor
    (Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.
    In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.
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    14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
    (Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.
    In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.
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    CCD Sensor Based Cameras for Sustainable Streaming IoT Applications With Compressed Sensing
    (Institute of Electrical and Electronics Engineers Inc., 2023) Gambheer, R.; Bhat, M.S.
    This paper presents a comprehensive study of compressed sensing (CS) techniques applied to Charge Coupled Device (CCD) and Complementary Metal-Oxide Semiconductor (CMOS) sensor-based cameras. CS is a powerful technique for reducing the number of measurements required to capture high-quality images while maintaining a high signal-to-noise ratio (SNR). In this study, we propose a novel CS method for CCD and CMOS sensor-based cameras that combines a new sampling scheme with a sparsity-inducing transform and a reconstruction algorithm to achieve high-quality images with fewer measurements. This paper focuses on an efficient CCD image capturing system suitable for embedded IoT applications. Hardware implementation has been done for proof of concept with an onboard Field Programmable Gate Array (FPGA) performing the compression. This hardware module is used over a wireless network to transmit and receive images under different test conditions with both CMOS and CCD sensors. For each use case, Peak Signal to Noise Ratio (PSNR), average power, and memory usage are computed under different ambient lighting conditions from dark to very bright. The results show that, a 640× 480 CCD sensor with compressed sensing with a sparsity of 0.5, provides 13% power saving and 15% memory saving compared to uncompressed sensing in no-light condition, resulting in 25.76 dB PSNR. Whereas, in no light condition, CMOS sensor does not capture any image at all. These results shows that the CCD image capturing system with compressed sensing can be conveniently used for embedded IoT applications. The data recovery from wireless sensor network is done at a central office where computing time and processing power resources are not constrained. The weight of the CCD camera is approximately 100 grams with modular build approach. © 2013 IEEE.