Faculty Publications
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Publications by NITK Faculty
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Item Design of resolution adaptive TIQ flash ADC using AMS 0.35 ?m technology(Inderscience Publishers, 2009) Rajashekar, G.; Bhat, M.S.This paper presents a resolution adaptive flash A/D converter design and its performance. To achieve high speed, the proposed A/D converter utilises threshold inverter quantisation technique replacing conventional analogue comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analogue nodes in the ADC. The proposed ADC is a true variable resolution ADC, operates at 3-bit, 4-bit, 5-bit and 6-bit precision depending on control inputs. The proposed ADC is designed with AMS 0.35 m CMOS technology and 3.3 V power supply voltage and a prototype chip is fabricated. Simulation results and test results are presented. Copyright © 2009, Inderscience Publishers.Item 11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.Item 14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique(Birkhauser, 2020) Polineni, P.; Bhat, M.S.; Rekha, S.In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of 568?m×298?m and consumes a power as less as 0.28?W. It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/? 0.84 least significant bit (LSB) and + 0.1/? 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications(John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.