Faculty Publications
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Item A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.Item A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture(IEEE Computer Society help@computer.org, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact switched capacitor integrator (SCI) based successive approximation register (SAR) analog to digital converter (ADC) for data acquisition system is presented. This technique requires an operational transconductor amplifier (OTA), a comparator and four equal sized capacitors of moderate value for fully differential approach and the architecture is resolution independent. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of a switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the SC integrating capacitor. ADC being fully differential nature has wide input range and it is parasitic insensitive to a large extent. As a stand alone data converter it has small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8 V supply, has effective number of bits (ENOB) of 9.5 at Nyquist frequency. The ADC occupies small die area compared to SAR with a binary weighted capacitor array. © 2019 IEEE.Item An Efficient AI-Based Classification of Semiconductor Wafer Defects using an Optimized CNN Model(Institute of Electrical and Electronics Engineers Inc., 2023) Pandey, C.; Bhat, K.G.Wafer maps used to display defect patterns in the integrated circuits industry include crucial information that quality engineers may utilize to identify the cause of a defect and increase yield. In this paper, we put forth a framework for accurately and quickly categorizing semiconductor wafer faults utilizing particularly CNN-based models. This paper seeks to provide a scalable, adaptive, and user-friendly implementation of convolutional neural networks for applications classifying semiconductor defects. In categorizing the defects found on semiconductor wafers, the suggested CNN model obtained an accuracy of 90.50% & 92.28% and losses of 0.39 & 0.29 while performing the training and validation, respectively, along with the misclassification rate of 0.0772. The suggested model also learns rapidly on the validation set at a rate of 1e-03 per second. The proposed custom CNN model architecture incorporates only two convolution layers, resulting in a greatly reduced number of parameter weights and biases. Specifically, the number of parameters is only 44000, which makes the model more compact, cost-effective, and robust against random noise. Moreover, this model can function well under low power and processing limits. © 2023 IEEE.Item High Gain Ultra-Low NF Wideband CMOS Low Noise Amplifier Design Using 2-Stage Series-Parallel LC Matching Network(Institute of Electrical and Electronics Engineers Inc., 2023) Sudhanva, P.V.C.S.; Yugandhar, B.; Kumar, S.; Kumar, K.; Bhat, K.G.The focus of this work is the development of a sub-6 GHz (2-6 GHz) low noise amplifier (LNA) for 5G applications, using a 65 nm CMOS process. A novel two stage common source (CS) cascode source degeneration LNA topology by incorporating a contemporary series parallel LC network and two stage LC network for input and output matching respectively is proposed. The circuit implementation, simulations and evaluation of the LNA's performance are done utilizing the RF Spectre Cadence Virtuoso. According to the evaluation results, the LNA dissipates a total power of 19.6 mW at the supply voltage of 0.7 V. It offers an operational wide bandwidth (BW) of 3.2 GHz which ranges from 2.8 GHz to 6 GHz. The LNA has a peak gain of 36 dB and minimum noise figure (NF) of 1.1 dB across the sub-6 GHz spectrum. The proposed LNA also performs well in terms of stability and linearity measures. The layout of the proposed LNA occupies an area of 0.182mm2 © 2023 IEEE.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.