Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Posit Extended RISC-V Processor and Its Enhancement Using Data Type Casting(Springer Science and Business Media Deutschland GmbH, 2023) Kurian, A.; Ramesh Kini, M.The Posit extended RISC-V processor has gained attention as an alternative to its floating point counterpart. However, the Posit compliant RISC-V processor needs further enhancements to be accepted as a standard. In this paper, the shortcomings of existing Posit integration approaches are discussed and a novel approach is put forth wherein, Posit and the floating point arithmetic are incorporated within the core. We also present a comparative study of various Posit integration approaches in terms of resource utilization and timing requirements. Furthermore, to enhance RISC-V processor that supports the concurrent usage of integer, floating point and the Posit arithmetic, a data type casting unit is incorporated. Two data type casting approaches are suggested and compared in terms of speed and the area occupied. Based on the implementation results, inferences are derived on the apt choice of data type casting approach to be undertaken. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.Item Designing, Implementing, and Interfacing BFloat16 Arithmetic Processing Unit to RISC-V Pipelined Processor(Springer Science and Business Media Deutschland GmbH, 2025) Shiva Ganesh, K.; Ramesh Kini, M.In this paper, we present the implementation of Brain floating point format (BFloat16) floating point arithmetic unit in the execute pipeline of the RISC-V processor. For a certain class of applications like deep neural networks, this format significantly improves the power, performance, and area (PPA) metrics of the processor as compared to a single precision format. To validate our approach, we developed a dedicated BFloat16 floating point arithmetic unit and conducted a comprehensive comparison with the conventional single precision floating point unit (FPU32). The BFloat16 format demonstrates a well-balanced trade-off between computational advantages and storage benefits when compared to the IEEE-754 single precision format. The proposed unit extends the capabilities of the RISC-V processor to efficiently handle BFloat16 computations, incorporates architectural modifications and instruction set extensions; achieving enhanced performance. Implementation on an Artix-7 FPGA (XC7a35tcpg236-1) allowed us to assess resource utilization and timing delay. Additionally, the arithmetic units of both formats are implemented on ASIC using gf180 PDK (process design kit) using OpenROAD toolchain. The results show that the BFloat16 unit consumes fewer resources and also computes faster than the existing FPU32 operations. The proposed BFloat16-compliant RISC-V core can run at a maximum frequency of 47 MHz with a power consumption of 0.075W. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.