Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Improved Algorithm for Minimum Power 2-Connected Subgraph Problem in Wireless Sensor Networks(Institute of Electrical and Electronics Engineers Inc., 2018) Lakshmi, M.; Shetty D, D.A Wireless Sensor Network (WSN) consists of small sensor nodes which communicate with each other using wireless radio channel and are used to monitor certain environmental parameters. Since the nodes are powered by a small battery of limited capacity, it is important to minimize the energy consumption in a WSN. By using an appropriate topology the energy utilization of the network can be minimized which results in an increased lifetime of a WSN. In practice, the transmission power of a sensor node can be tuned to obtain a required topology that satisfies certain connectivity constraints and this problem is known as Range Assignment Problem. For a given network, a reduced topology is constructed satisfying some connectivity constraints like k-connectivity, bounded diameter etc. Fault tolerance addresses the issue of node or link failure which aims at k-connectivity so that, the network has at least k vertex disjoint paths between any two nodes of the network. With the motivation of achieving fault tolerant network with minimum transmission energy, we consider Minimum power 2-connected subgraph (MP2CS) problem which is proved to be NP-hard. A polynomial time heuristic is proposed in this paper for the MP2CS problem and simulation is performed to compare with the existing algorithm. © 2018 IEEE.Item Design of an adaptive and reliable network on chip router architecture using FPGA(Institute of Electrical and Electronics Engineers Inc., 2019) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.We propose an adaptive, low cost, reliable and high performance router implemented based on a conventional two stage pipeline. The proposed Adaptive routing operates in adaptive mode as soon as the congestion is detected in network. We employ fault tolerant strategies for different components of routers such as input buffer, route compute unit, virtual channel allocation, switch allocation, and crossbar unit. The proposed router architecture differs from existing reliable routers, our implementation maintains the performance of fault tolerance router under massive network workloads by influencing the features of a crossbar, routing algorithm and router pipeline optimization. Our designed router is highly reliable than current fault receptive routers such as Wang[1], Vicis[2], BulletProof[3], RoCo[4] and Poluri[5]. The average latency is reduced by 0.69% and increased by 2.0% compared to fault tolerant and conventional router. © 2019 IEEE.