Conference Papers

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506

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    Speed control of BLDC motor using bridgeless SEPIC PFC with coupled inductors
    (Institute of Electrical and Electronics Engineers Inc., 2016) Prabhu, P.; Vinatha Urundady, U.
    In this paper Bridgeless (BL) Sepic PFC with Coupled Inductors (CIs) is proposed for controlling the DC voltage of Three phase VSI to control the speed of BLDC motor. DC voltage control method enables 3 phase VSI to operate at fundamental frequency and thus reduces switching losses. Sepic converter provides output voltage of positive polarity and allows both step up and step down of input voltage in order to facilitate for the speed control of motor over a wide range. Discontinuous Conduction Mode (DCM) operation of Sepic converter, automatically shapes input current. Thus provides inherent Power Factor Correction (PFC). Also it eliminates the necessity of inner current loop and thereby reduces the number of sensors required. For the same power requirement, if CIs are introduced in the power circuit of BL Sepic, it results in reduction in size and cost of the system. This also gives improved efficiency due to the reduction in core loss. 500 W BL Sepic PFC with CIs is designed ensuring its operation in DCM to supply DC voltage in the range 70 V-310 V for a BLDC motor rated 375 W, 310 V and 3000 rpm. The proposed system is simulated for above range of voltages and performance is analysed. Results indicate that BL Sepic with CIs gives better performance with regard to efficiency and THD in addition to the reduction in overall size of converter. © 2016 IEEE.
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    Single inductor dual output buck converter for low power applications and its stability analysis
    (IEEE Computer Society help@computer.org, 2018) Sankaranarayanan, S.; Vinod, K.C.; Sreekumar, A.; Laxminidhi, L.; Singhal, V.; Chauhan, R.
    The applications like sensor nodes and wearables, which run on coin/button cell and/or harvested energy source need small form factor and very low power consumption. A single inductor multiple output (SIMO) converter provides saving on inductor count and hence becomes a right choice for such applications. This paper presents a single inductor dual output (SIDO) buck converter targeting light load applications. The architecture uses discontinuous conduction mode (DCM) with pulse frequency modulation (PFM) control and the switching scheme ensures almost zero cross-regulation. The proposed converter is simulated in 180 nm CMOS technology showing zero cross-regulation. An efficiency of above 88% is achieved considering inductor and package losses in load range of micro-Amperes to a few milli-Amperes. This paper also presents a detailed stability analysis and model for the selected SIMO architecture along with some interesting observations and inferences derived from this analysis. © 2018 IEEE.
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    Hardware Co-simulation of Pulse Amplitude Modulation Controlled BLDC Motor
    (Institute of Electrical and Electronics Engineers Inc., 2022) Prabhu, P.; Kulkarni, S.V.; Urundady, V.
    This paper describes the validation of a Field Programmable Gate Array (FPGA)-based controller for Brushless Direct Current (BLDC) motor drive using the hardware co-simulation feature enabled in the Xilinx System Generator (XSG) design tool. To control the speed of the BLDC motor, the proposed BLDC drive uses PAM control of the Voltage Source Inverter (VSI). The PAM control reduces switching losses by allowing the VSI to operate at the frequency determined by synchronous speed. At the front end, a bridgeless SEPIC provides a wide range of DC voltage to the VSI input. When compared to the topology with two separate inductors, the Bridgeless SEPIC coupled inductors reduce the overall component count and the self-inductance required. The converter is designed to operate in Discontinuous Conduction Mode (DCM) by applying a simple voltage follower approach to a SEPIC converter to achieve inherent input current shaping over a wide speed range. The precise reference voltage for the DC link is calculated in the outer speed control loop. The proposed BLDC motor drive is modeled using the XSG design tool, and the controller is implemented in FPGA. Hardware co-simulation is used to evaluate the controller's performance under dynamic conditions such as step changes in reference speed and supply voltage. © 2022 IEEE.