Conference Papers

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    Sample-based DC prediction strategy for HEVC lossless intra prediction mode
    (Institute of Electrical and Electronics Engineers Inc., 2017) Kamath, S.S.; Aparna., P.; Antony, A.
    High-Efficiency Video Coding (HEVC), the state-of-the-art video coding standard by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group, is presently being prepared to handle the next generation multi-media services. Lossless mode of HEVC is designed to support a variety of lossless compression applications like medical imaging, preservation of artwork, video analytics, etc. The accuracy of the intra prediction can be improved through the incorporation of sample-based prediction strategies which replace the block-based prediction within HEVC. In this work, we propose a sample-based DC intra prediction strategy to enhance the compression efficiency of the HEVC lossless mode. The detailed experimental analysis demonstrates that the proposed method outperforms the HEVC lossless mode of HM16.12 in terms of bit-rate savings by 1.43% and 0.46% on an average for AI-Main and AI-Main10 configurations respectively, without any increase in run-time. © 2017 IEEE.
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    Efficient architectures for planar and DC modes of intra prediction in HEVC
    (Institute of Electrical and Electronics Engineers Inc., 2020) Lakshm; I Aparna., P.
    High efficiency video coding (HEVC) handles the ever increasing global video content with better compression efficiency. Complex partition and increased number of angular modes in intra prediction is one of the factors responsible to achieve this but at the expense of complex computations. In this work, we propose two hardware architectures, Parallel Pipelined Architecture (PPA), and Parallel Datapath Architecture (PDA) for the planar and direct current (DC) modes of intra prediction in HEVC. PPA supports a combination of pipelining and parallel schemes, reuses the multipliers to reduce the hardware resources. PDA includes datapath0 for planar mode and datapath1 for DC mode. They function in parallel. They support all the block sizes and implemented on Artix-7 field programmable gate array (FPGA). The implemented results show that PDA uses 20% fewer resources for block size 4, while PPA uses 20%, 46%, and 62% fewer resources for block sizes 8, 16, and 32, respectively. Detailed synthesis results show that PPA and PDA achieve a throughput of 8 pixels/clock cycle and hence can support 4K videos at 30 frames per second. © 2020 IEEE.