Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Cache analysis and software optimizations for faster on-chip network simulations(Institute of Electrical and Electronics Engineers Inc., 2016) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.Fast simulations are critical in reducing time to market in CMPs and SoCs. Several simulators have been used to evaluate the performance and power consumed by Network-on-Chips. Researchers and designers rely upon these simulators for design space exploration of NoC architectures. Our experiments show that simulating large NoC topologies take hours to several days for completion. To speedup the simulations, it is necessary to investigate and optimize the hotspots in simulator source code. Among several simulators available, we choose Booksim2.0, as it is being extensively used in the NoC community. In this paper, we analyze the cache and memory system behaviour of Booksim2.0 to accurately monitor input dependent performance bottlenecks. Our measurements show that cache and memory usage patterns vary widely based on the input parameters given to Booksim2.0. Based on these measurements, the cache configuration having least misses has been identified. We also employ thread parallelization and vectorization to improve the overall performance of Booksim2.0. The OpenMP programming model and SIMD are used for parallelizing and vectorizing the more time-consuming portions of Booksim2.0. Speedups of 2.93× and 3.97× were observed for the Mesh topology with 30 × 30 network size by employing thread parallelization and vectorization respectively. © 2016 IEEE.Item FPGA based NoC Simulation Acceleration Framework Supporting Adaptive Routing(Institute of Electrical and Electronics Engineers Inc., 2018) Parane, K.; Prabhu Prasad, B.M.; Talawar, B.In this paper, we present fast and param-eterized FPGA based Network-on-Chip (NoC) simu-lation acceleration framework with automated HDL generation engine. The framework supports the NoC architecture design parameters such as topology, rout-ing algorithms, link width, buffer size, flow control and traffic patterns. The parameterized, high perfor-mance and lightweight nature of proposed NoC based framework makes the ideal choice for NoC research studies. The Mesh based topologies have been con-sidered for the experimentation purpose. A congestion aware adaptive routing has been proposed along with the conventional XY routing. Also, parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on the NoC behavior. The adaptive routing algorithm for Mesh based topologies has negligible FPGA area overhead compared to the conventional XY routing. Employing the adaptive routing algorithm, the average packet latency is reduced by 55 % under transpose traffic pattern when compared to the XY routing algorithm. The speedup of 2548x has been observed compared to Booksim software simulator. The proposed framework is 2.54x and 25x times faster compared to CONNECT and DART FPGA based simulators respectively. © 2018 IEEE.Item Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks(Institute of Electrical and Electronics Engineers Inc., 2018) Kumar, A.; Talawar, B.Chip Multiprocessors(CMPs) and Multiprocessor System-on-Chips(MPSoCs) are meeting the ever increasing demand for high performance in processing large scale data and applications. There is a corresponding increase in the volume and frequency of traffic in the Network-on-Chip(NoC) architectures like CMPs and SoCs. NoC performance parameters like network latency, flit latency and hop count are critical measures which directly influence the overall performance of the architecture and execution time of the application. Unfortunately, cycle-accurate software simulators become slow for interactive use with an increase in architectural size of NoC. In order to provide the chip designer with an efficient framework for accurate measurements of NoC performance parameters, we propose a Machine Learning(ML) framework. Which is designed using different ML regression algorithms like Support Vector Regression(SVR) with different kernels and Artificial Neural Networks(ANN) with different activation functions. The proposed learning framework can be used to analyze the performance parameters of Mesh and Torus based NoC architectures. Results obtained are compared against the widely used cycle-accurate Booksim simulator. Experiments were conducted by variables like topology size from 2\times 2 to 30\times 30 with different virtual channels, traffic patterns and injection rates. The framework showed an approximate prediction error of 5% to 8% and overall minimum speedup of 1500\times to 2000\times. © 2018 IEEE.Item Floorplan Based Performance Estimation of Network-on-Chips using Regression Techniques(Institute of Electrical and Electronics Engineers Inc., 2019) Kumar, A.; Talawar, B.An intra-communication problem between the Intellectual Properties(IPs) caused by the growth of a number of cores on single chips in System-on-Chip(SoC) gave rise to new a system architecture called Network-on-Chip(NoC). The early stages of designing NoC can be done using cycle-accurate NoC simulators, but they become slow as the architecture size of NoC increases. Hence a machine learning framework is being proposed by considering two scenarios i,e. A fixed delay between the components and floorplan based delay among the components of NoC. This framework is modeled using distinct Machine Learning(ML) regression algorithms to predict performance parameters of NoCs considering uniform random and transpose traffic patterns. Complete performance analysis of Mesh NoC architecture can be done by using the proposed ML framework. Booksim simulator results are used to verify effectiveness of proposed framework and it showed an overall speedup of 2000× to 2500×. © 2019 IEEE.Item Accurate Router Level Estimation of Network-on-Chip Architectures using Learning Algorithms(Institute of Electrical and Electronics Engineers Inc., 2019) Kumar, A.; Talawar, B.The problem of intra-communication between the Intellectual Properties(IPs) due to the rise in the amount of cores on single chips in System-on-Chip(SoC). Network-on-Chips(NoCs) has emerged as a reliable on-chip communication framework for Chip Multiprocessors and SoCs. Estimating NoC power and performance in the early stages has become crucial. We employ Machine Learning(ML) approaches to estimate architecture-level on-chip router models and performance. Experiments were carried out with distinct topology sizes with various virtual channels, injection rates, and traffic patterns. Booksim and Orion simulators are used to validate the results. Approximately 6% to 8% prediction error and a minimum speedup of 1500 × to 2000 × were shown in the framework. © 2019 IEEE.Item A Support Vector Regression-Based Approach to Predict the Performance of 2D 3D On-Chip Communication Architectures(Institute of Electrical and Electronics Engineers Inc., 2019) Nirmal Kumar, A.; Talawar, B.Recently, Networks-on-Chips (NoCs) have evolved as a scalable solution to traditional bus and point-to-point architecture. NoC design performance evaluation is largely based on simulation, which is extremely slow as the architecture size increases, and it gives little insight on how distinct design parameters impact the actual performance of the network. Simulation for optimization purposes is therefore very difficult to use. In this paper, we propose a Support Vector Regression(SVR)-based framework, which can be used to analyze the performance of 2D and 3D NoC architectures. Experiments were conducted by varying architecture sizes with different virtual channels, injection rates. The framework proposed can be used to obtain fast and accurate NoC performance estimates with a prediction error 2% to 4% and minimum speedup of 3000 × to 3500×. © 2019 IEEE.Item UPM-NoC: Learning based framework to predict performance parameters of mesh architecture in on-chip networks(Springer, 2020) Kumar, A.; Talawar, B.Conventional Bus-based On-Chips are replaced by Packet-switched Network-on-Chip (NoC) as a large number of cores are contained on a single chip. Cycle accurate NoC simulators are essential tools in the earlier stages of design. Simulators which are cycle accurate performs gradually as the architecture size of NoC increases. NoC architectures need to be validated against discrete synthetic traffic patterns. The overall performance of NoC architecture depends on performance parameters like network latency, packet latency, flit latency, and hop count. Hence we propose a Unified Performance Model (UPM) to deliver precise measurements of NoC performance parameters. This framework is modeled using distinct Machine Learning (ML) regression algorithms to predict performance parameters of NoCs considering different synthetic traffic patterns. The UPM framework can be used to analyze the performance parameters of Mesh NoC architecture. Results obtained were compared against the widely used cycle accurate Booksim simulator. Experiments were conducted by varying topology size from 2×2 to 50×50 with different virtual channels, traffic patterns, and injection rates. The framework showed an approximate prediction error of 5% to 6% and overall minimum speedup of 3000× to 3500×. © Springer Nature Singapore Pte Ltd 2020.Item Hy-BTree: An efficient Tree based topology for FPGA based NoC implementation(Institute of Electrical and Electronics Engineers Inc., 2021) Prabhu Prasad, B.M.; Parane, K.; Talawar, B.Due to their hierarchical structure, Binary Tree (BTree) topology can be employed in Network-on-Chip (NoC) applications. Because of its lower bisection bandwidth, the performance degradation is observed in communication intensive applications. The Fat tree topology has been proposed to overcome the disadvantages of the BTree topology. But, the complexity of the Fat Tree topology's router becomes more complicated as we move towards the root node of the tree and occupying a huge amount of hardware resources compared to the BTree variant. Instead of going for Fat Tree topology, the number of hops taken by a packet in the BTree topology can be reduced by introducing new links in the network with an increase in the bisection bandwidth. In this work, we propose a variant of BTree topology called Hy-BTree by introducing additional links at the intermediate levels of the network to reduce the number of hops taken for the communication. The proposed design is implemented on the FPGA and compared with the other topologies from state-of-the-art the FPGA based NoC architectures. A reduction in average latency and an improvement in throughput have been observed in Hy-BTree with respect to the BTree network with negligible overhead. © 2021 IEEE.