Conference Papers
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Item FPGA based experimental evaluation of BLDC motor drive fed from coupled inductor based bridgeless SEPIC(Institute of Electrical and Electronics Engineers Inc., 2020) Prabhu, P.; Vinatha Urundady, U.This paper presents FPGA based experimental evaluation of BLDC motor drive fed from single-phase supply through coupled inductor based bridgeless SEPIC converter. This converter supplies an adjustable DC link voltage to the input of three-phase VSI, which serves as electronic commutator for the BLDC motor. The VSI is switched at the fundamental frequency determined by rotor position, and the variable DC link voltage provides adjustable speed (N\propto V-{dc}) in the proposed BLDC motor drive. The incorporation of coupled inductors for bridgeless SEPIC achieves compactness. The converter with coupled inductors ensures a similar performance with reduced size as that of the conventional bridgeless SEPIC. The bridgeless SEPIC incorporating coupling presented in this work has the improved features of compact size, reduced structure complexity, requirement of only one low side gate driver and the absense of circulating current. The converter can provide both supply current shaping and control of output voltage with only voltage control loop. The Artix 7, Xilinx FPGA is used to implement the control system consisting of electronic commutation logic for switching the VSI and PI controller based DC link voltage controller for switching the proposed front end converter. The control logic is implemented using Xilinx System Generator (XSG), model-based design tool in MATLAB/Simulink environment. The XSG model-based design is processed in Vivado Design Suite software to generate programmable bit file for FPGA. The experimental results are obtained to validate the achievement of adjustable speed and shaping of supply current in the proposed BLDC motor drive. © 2020 IEEE.Item Ripple Current Reduction of Double-Gain SEPIC Converter Using Coupled Inductor(Institute of Electrical and Electronics Engineers Inc., 2022) Diwakar Naik, M.D.; Vinatha Urundady, U.In this paper Input current ripple reduction technique of a Double-Gain SEPIC (DGSEPIC) converter using Coupled Inductor (CI) is proposed. This converter can provide buck-boost non-inverting output voltage by maintaining continuous input current. The voltage gain of this converter is twice that of a conventional SEPIC converter, so this converter is capable of providing a wide range of output voltage variations by changing the converter's duty cycle. The input ripple current of the converter is reduced using CI, which eliminates the use of a high-rating filter circuit at the input side of the converter. This converter needs a single switch and a few additional inductors and capacitors to obtain twice the voltage gain. Since the converter has only one switch, the complexity of the controller design is less. A PI (Proportional and Integral) controller with Pulse Width Modulation (PWM) technique is used to control the gate pulses of the converter. The simulation of the converter is done using MATLAB/Simulink software, and the results of the Double gain SEPIC converter with CI are presented. © 2022 IEEE.