Conference Papers
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Item Accurate Router Level Estimation of Network-on-Chip Architectures using Learning Algorithms(Institute of Electrical and Electronics Engineers Inc., 2019) Kumar, A.; Talawar, B.The problem of intra-communication between the Intellectual Properties(IPs) due to the rise in the amount of cores on single chips in System-on-Chip(SoC). Network-on-Chips(NoCs) has emerged as a reliable on-chip communication framework for Chip Multiprocessors and SoCs. Estimating NoC power and performance in the early stages has become crucial. We employ Machine Learning(ML) approaches to estimate architecture-level on-chip router models and performance. Experiments were carried out with distinct topology sizes with various virtual channels, injection rates, and traffic patterns. Booksim and Orion simulators are used to validate the results. Approximately 6% to 8% prediction error and a minimum speedup of 1500 × to 2000 × were shown in the framework. © 2019 IEEE.Item A Support Vector Regression-Based Approach to Predict the Performance of 2D 3D On-Chip Communication Architectures(Institute of Electrical and Electronics Engineers Inc., 2019) Nirmal Kumar, A.; Talawar, B.Recently, Networks-on-Chips (NoCs) have evolved as a scalable solution to traditional bus and point-to-point architecture. NoC design performance evaluation is largely based on simulation, which is extremely slow as the architecture size increases, and it gives little insight on how distinct design parameters impact the actual performance of the network. Simulation for optimization purposes is therefore very difficult to use. In this paper, we propose a Support Vector Regression(SVR)-based framework, which can be used to analyze the performance of 2D and 3D NoC architectures. Experiments were conducted by varying architecture sizes with different virtual channels, injection rates. The framework proposed can be used to obtain fast and accurate NoC performance estimates with a prediction error 2% to 4% and minimum speedup of 3000 × to 3500×. © 2019 IEEE.