Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Manpower development in VLSI ni India: A case study(Institute of Electrical and Electronics Engineers Inc., 2003) Shet, K.C.In this paper a review of development of manpower in VLSI in India is attempted. In the last decade of the 20th Century, rapid strides have been done in Micro-Electronics in India. Both private and public institutions have accelerated the growth of VLSI, Chip design and embedded systems including DSP. © 2003 IEEE.Item Authentication based on bioinformatics(2004) Mohandas, M.K.; Shet, K.C.Authentication has assumed a lot of importance over the years due to hackers and unauthorised access. The Authentication based on bioinformatics will do away with all kinds of smart cards, identity cards or any other device being carried by the users. A lot of research is being done to improve the reliability of bioinformatics comparison with central database. This paper focuses on the research carried at NITK, Surathkal in this direction.Item Activity-based software estimation using work break down structure(Kluwer Academic Publishers, 2007) Basavaraj, M.J.; Shet, K.C.Software Cost estimation at activity level is very much accurate than macro estimation with respect to phases of software development life cycle, but the same is very difficult to achieve[1]. Activity based estimation focus on key activities should not be left out and if any effort variance occurs it will be possible to track at particular activity level rather than affecting the entire activities[1]. Activity-based Software estimation based on work break down structure has been explained by collecting and analyzing the data for 12 Enhancements from Application service Maintenance project which were already delivered. This paper explains how to arrive accurate estimation at different micro level activities of Software Development Life Cycle(SDLC). © 2007 Springer.Item Software estimation using function point analysis: Difficulties and research challenges(Kluwer Academic Publishers, 2007) Basavaraj, M.J.; Shet, K.C.Function Point Analysis method serves better efficient way of predicting estimation in beginning phase of software development life cycle(SDLC). Size and complexity of the software can be derived by function point analysis method. Difficulties of estimation using LOC(Lines of Code) can be avoided using Function Point Analysis, since it deals directly with functions or requirements and independent of language or technology. This paper explains how to calculate Function point analysis for the case study Defect Tracking System(DTS) by using function point analysis. Defect tracking system(DTS) case study has been taken from "XYZ" company. In the intention of maintaining confidentiality, authors are not disclosing the company name. Authors also discusses difficulties and challenges by using Function Point Analysis as part of their Research Work. © 2007 Springer.Item Development of scheduler for real time and embedded system domain(2008) Rao, M.V.P.; Shet, K.C.; Balakrishna, R.; Roopa, K.We discuss scheduling techniques to be used for real-time, embedded systems. Though there are several scheduling policies, the preemptive scheduling policy holds promising results. In this research paper, the different approaches to design of a scheduler for real-time Linux kernel are discussed in detail. The comparison of different preemptive scheduling algorithms is performed. Hence, by extracting the positive characteristics of each of these preemptive scheduling policies, a new hierarchical scheduling policy is developed. The proposed hierarchical scheduling for real time and embedded system will be implemented for a prototype system, using C or C++ language. It is expected that the new scheduling algorithm will give better performance with respect to satisfy the needs, such as time, capturing and usage of resources of different applications. © 2008 IEEE.Item Verification framework for detecting safety violations in UML statecharts(2008) Prashanth, C.M.; Shet, K.C.; Elamkulam, J.The model based development is a widely accepted phenomenon to build dependable software. This has lead to development of tools which can generate deployable code from the model. Hence, ensuring the correctness of such models becomes extremely important. Model checking technique can be applied to detect specification violations in such models at the early stage of development life cycle. In practice, such validations are done using off-the-shelf model checkers. This technique though popular has a drawback that, model should be described in the native language of the model checker. In this paper, we propose a framework for the verification of the dynamic behavior of reactive systems modeled using UML (Unified Modeling Language) statechart diagrams. The model is translated to an intermediate representation by parsing the information embedded behind the UML Statecharts, this intermediate representation is used for checking the safety violations. Verification framework proposed is scalable to complex systems. © 2008 IEEE.Item Key management using k-dimensional trees(2008) Renuka, R.; Shet, K.C.In this paper we present a protocol for group key management in mobile ad hoc networks based on K-dimensional trees, a space partitioning data structure. We use a 2- dimensional tree for a 2 dimensional space. The 2 dimensional tree resembles a binary tree. The protocol reduces the memory requirements for storing the tree by nearly 50% compared to the existing methods and also reduces the number of key changes required whenever membership changes occur. © 2008 IEEE.Item An efficient event based approach for verification of UML statechart model for reactive Systems(2008) Prashanth, C.M.; Shet, K.C.; Elamkulam, J.Abstract-This paper describes an efficient method to detect safety specification violations in dynamic behavior model of concurrent/reactive systems. The dynamic behavior of each concurrent object in a reactive system is assumed to be represented using UML (Unified Modeling Language) statechart diagram. The verification process involves building a global state space graph from these independent statechart diagrams and traversal of large number of states in global state space graph for detecting a safety violation. In our approach, a safety property to be verified is read first and a set of events, which could violate this property, is computed from the model description. We call them as "relevant events". The global state space graph is constructed considering only state transitions caused by the occurrence of these relevant events. This method reduces the number of states to be traversed for finding a property violation. Hence, this technique scales well for complex reactive systems. As a case study, the proposed technique is applied to verification of Generalized Railroad Crossing (GRC) system and safety property "When train is at railroad crossing, the gate always remain closed" is checked. We could detect a flaw in the infant UML model and eventually, correct model is built with the help of counter example generated. The result of the study shows that, this technique reduces search space by 59% for the GRC example. © 2008 IEEE.Item NATR: A new algorithm for tracing routes(2008) Prasad, G.R.; Shet, K.C.; Bhat Narasimha, B.This paper presents NATR ("New Algorithm for Tracing Routes"), a new shortest path algorithm using reconfigurable logic and has time complexity O(L), where L is shortest path length. It uses ball and string model and is highly parallel and scalable. Unlike most other shortest path algorithms, NATR does not need to find the minimum of nodes/adjacent nodes. Hence its FPGA implementation is faster compared to other FPGA implementations. Preliminary experimental results show that a 17-node NATR runs about 6.3 times faster compared to parallel Bellman-Ford algorithm on Xilinx Virtex II. © Springer Science+Business Media B.V. 2008.Item GRASP: A greedy reconfigurable approach for shortest path(2008) Prasad, G.R.; Shet, K.C.; Bhat Narasimha, B.This paper presents GRASP ("Greedy Reconfigurable Approach for Shortest Path"), a new shortest path algorithm using reconfigurable logic. It has time complexity O(P), where 'P' is maximum of number of edges along the shortest paths from source to other nodes. It is a modification of Bellman-Ford algorithm and is highly parallel and scalable. Unlike most other shortest path algorithms, GRASP does not need to find the minimum of nodes/adjacent nodes. Hence its FPGA implementation is faster compared to other FPGA implementations. Preliminary experimental results show that a 17-node GRASP runs about 4.7 times faster compared to parallel Bellman-Ford algorithm on Xilinx Virtex II. © Springer Science+Business Media B.V. 2008.