Conference Papers
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Item Modeling of Human Face Expressions and Hand Movement for Animation(Institute of Electrical and Electronics Engineers Inc., 2018) Sangeetha, G.S.; Koolagudi, S.G.; Ramteke, P.B.; Singala, S.; Sastry, S.Animation is the process of creating an illusion of motion by moving images rapidly in an order which minimally differ from each other. In this paper, a solution is proposed to simplify the process of animation by tracking movement of hand and facial expressions. Face detection performed using Haar-Cascade classifier whereas hand detection is achieved using Otsu's binarization and Ramer-Douglas-Peucker contour detection algorithm. Facial expression landmarks are captured from the Haarlike features. Hand movements feature points are extracted from the contour. Replay phase includes drawing the virtual object by calculating the translational factors and redrawing the virtual object in every frame during replay. The proposed approach is observed to achieve the smooth translation of face expression and hand movement and reduce the time and effort needed to make the animation. Copy Right © INDIACom-2018.Item Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA(Institute of Electrical and Electronics Engineers Inc., 2018) Sangeetha, G.S.; Radhakrishnan, V.; Prabhu Prasad, P.; Parane, K.; Talawar, B.Networking On Chips is now becoming an extremely important part of the present and future of electronic technology. It is extensively used in Multiprocessor System-on-Chips and in Chip Multiprocessors. Using an NoC, the backend wiring involved has drastically reduced in an SoC. Further, SoCs with NoC interconnect operates at a higher operating frequency, mainly because the hardware required for switching and routing are simplified. The NoC researchers have relied on simulators based on performance and power to study the different factors of NoC such as algorithm in place, the topology, the buffer management and location schemes, the flow control and routing among others. In this paper, we present a trace-driven NoC architecture that gives the user access to realistic details about the resource utilization of NoC architectures and their individual components. This includes exploration of various design decision parameters of NoC by modeling them on a FPGA. The paper also presents the performance of these architectures by conducting trace-driven simulations using benchmarks like PARSEC. Different topologies are considered for experimentation purposes with different routing algorithms. © 2018 IEEE.