Conference Papers
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Item YaNoC: Yet another network-on-chip simulation acceleration engine using FPGAS(IEEE Computer Society help@computer.org, 2018) Parane, K.; Talawar, B.; Prabhu Prasad, P.In this paper, we present an FPGA based NoC simulation framework, YaNoC, that supports the creation of standard and custom topologies, design of routing algorithms, generation of various synthetic traffic patterns, and exploration of a full set of microarchitectural parameters. The framework supports all standard minimal routing algorithms for conventional NoCs and implements table based routing to support the creation of new routing algorithm. A custom topology called Diagonal Mesh (DMesh) has been evaluated using table based and a modified version of the XY routing algorithm. Mesh and DMesh topologies saturate at the injection rates of 45 % and 55 %. We find that the Table based routing implementation consumes 0.98× fewer hardware resources than the conventional XY routing. We observed the speedup of 2548× compared to the Booksim software simulator. YaNoC achieves speedup of 2.54× and 25× with respect to CONNECT and DART FPGA based NoC simulators. © 2018 IEEE.Item Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA(Institute of Electrical and Electronics Engineers Inc., 2018) Sangeetha, G.S.; Radhakrishnan, V.; Prabhu Prasad, P.; Parane, K.; Talawar, B.Networking On Chips is now becoming an extremely important part of the present and future of electronic technology. It is extensively used in Multiprocessor System-on-Chips and in Chip Multiprocessors. Using an NoC, the backend wiring involved has drastically reduced in an SoC. Further, SoCs with NoC interconnect operates at a higher operating frequency, mainly because the hardware required for switching and routing are simplified. The NoC researchers have relied on simulators based on performance and power to study the different factors of NoC such as algorithm in place, the topology, the buffer management and location schemes, the flow control and routing among others. In this paper, we present a trace-driven NoC architecture that gives the user access to realistic details about the resource utilization of NoC architectures and their individual components. This includes exploration of various design decision parameters of NoC by modeling them on a FPGA. The paper also presents the performance of these architectures by conducting trace-driven simulations using benchmarks like PARSEC. Different topologies are considered for experimentation purposes with different routing algorithms. © 2018 IEEE.