Conference Papers
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Item FPGA based experimental evaluation of BLDC motor drive fed from coupled inductor based bridgeless SEPIC(Institute of Electrical and Electronics Engineers Inc., 2020) Prabhu, P.; Vinatha Urundady, U.This paper presents FPGA based experimental evaluation of BLDC motor drive fed from single-phase supply through coupled inductor based bridgeless SEPIC converter. This converter supplies an adjustable DC link voltage to the input of three-phase VSI, which serves as electronic commutator for the BLDC motor. The VSI is switched at the fundamental frequency determined by rotor position, and the variable DC link voltage provides adjustable speed (N\propto V-{dc}) in the proposed BLDC motor drive. The incorporation of coupled inductors for bridgeless SEPIC achieves compactness. The converter with coupled inductors ensures a similar performance with reduced size as that of the conventional bridgeless SEPIC. The bridgeless SEPIC incorporating coupling presented in this work has the improved features of compact size, reduced structure complexity, requirement of only one low side gate driver and the absense of circulating current. The converter can provide both supply current shaping and control of output voltage with only voltage control loop. The Artix 7, Xilinx FPGA is used to implement the control system consisting of electronic commutation logic for switching the VSI and PI controller based DC link voltage controller for switching the proposed front end converter. The control logic is implemented using Xilinx System Generator (XSG), model-based design tool in MATLAB/Simulink environment. The XSG model-based design is processed in Vivado Design Suite software to generate programmable bit file for FPGA. The experimental results are obtained to validate the achievement of adjustable speed and shaping of supply current in the proposed BLDC motor drive. © 2020 IEEE.Item Hardware Co-simulation of Pulse Amplitude Modulation Controlled BLDC Motor(Institute of Electrical and Electronics Engineers Inc., 2022) Prabhu, P.; Kulkarni, S.V.; Urundady, V.This paper describes the validation of a Field Programmable Gate Array (FPGA)-based controller for Brushless Direct Current (BLDC) motor drive using the hardware co-simulation feature enabled in the Xilinx System Generator (XSG) design tool. To control the speed of the BLDC motor, the proposed BLDC drive uses PAM control of the Voltage Source Inverter (VSI). The PAM control reduces switching losses by allowing the VSI to operate at the frequency determined by synchronous speed. At the front end, a bridgeless SEPIC provides a wide range of DC voltage to the VSI input. When compared to the topology with two separate inductors, the Bridgeless SEPIC coupled inductors reduce the overall component count and the self-inductance required. The converter is designed to operate in Discontinuous Conduction Mode (DCM) by applying a simple voltage follower approach to a SEPIC converter to achieve inherent input current shaping over a wide speed range. The precise reference voltage for the DC link is calculated in the outer speed control loop. The proposed BLDC motor drive is modeled using the XSG design tool, and the controller is implemented in FPGA. Hardware co-simulation is used to evaluate the controller's performance under dynamic conditions such as step changes in reference speed and supply voltage. © 2022 IEEE.