Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Investigations on the Effect of Spacer Dielectrics on the DC Characteristics of Dual Material Gate Junctionless FinFETs(Institute of Electrical and Electronics Engineers Inc., 2020) Mathew, S.; Nithin, N.; Rao, R.This work analyses the influence of dielectric constant of spacer on the electrical characteristics as well as on two vital short channel effect parameters i.e DIBL and Subthreshold Swing of Dual Material Gate Junctionless FinFET (DMG-JLFinFET). Various spacer materials each with different dielectric constant, were used for 3D TCAD simulations. It was observed that high κ spacers gave higher value of ON current. Increase in leakage current was also observed for high κ spacers at higher negative gate bias. Subthreshold Swing (SS) as well as Drain Induced Barrier Lowering (DIBL) had reduced extensively with the increase in dielectric constant of spacer. © 2020 IEEE.Item Investigations on the effect of Dual Material Gate work function on DIBL and Subthreshold Swing in Junctionless FinFETs(Institute of Electrical and Electronics Engineers Inc., 2020) Mathew, S.; Nithin; Bhat, K.N.; Rao, R.This paper investigates the influence of gate material work function on the electrical characteristics as well as short channel effects exhibited by Dual Material Gate-Junctionless FinFETs (DMG-JLFinFETs) with channel length as low as 10 nm. 3D TCAD simulations performed on these devices show that various device parameters like threshold voltage, ON-current, etc, are influenced by the work function difference between the control gate and screen gate material of DMG-JLFinFET. DMG-JLFinFETs exhibit very low Drain Induced Barrier Lowering (DIBL), far lesser than its Single Material Gate (SMG) counterpart. Subthreshold Swing (SS) of DMG devices is higher than SMG devices. The optimal ratio of control gate length to total gate length in DMG-JLFinFET is found to be between 0.5 and 1 for better suppression of short channel effects. © 2020 IEEE.Item An Exploration of the Effective Path for Current Conduction in a Triple Gate Junctionless FinFET(Institute of Electrical and Electronics Engineers Inc., 2023) Chennamadhavuni, S.; Mathew, S.; Rao, R.The goal of this work is to exclusively investigate the effective path for current conduction in the channel of a Triple Gate (TG) Silicon-ON-Insulator (SOI) Junctionless Fin Field Effect Transistor (JLFinFET). It is observed that various structural parameters play a key role in deciding the location of the effective current path both in full depletion mode and partial depletion mode in TG SOI JLFinFET. Considering the present day technology requirements 20 nm was chosen as the gate length. Simulations performed using 3-D TCAD namely ATLAS by Silvaco Inc. reveal that the conducting path from source to drain starts from nearer to the centre of the channel (i.e, at half the fin height and half the fin width) when the transistor switches from the OFF state to the ON state. It is also observed that when the triple gate transistor scales down in size the capacitive coupling between the top gate and side gates is a crucial factor in determining the location of the effective current path. © 2023 IEEE.