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Item Efficient architectures for planar and DC modes of intra prediction in HEVC(Institute of Electrical and Electronics Engineers Inc., 2020) Lakshm; I Aparna., P.High efficiency video coding (HEVC) handles the ever increasing global video content with better compression efficiency. Complex partition and increased number of angular modes in intra prediction is one of the factors responsible to achieve this but at the expense of complex computations. In this work, we propose two hardware architectures, Parallel Pipelined Architecture (PPA), and Parallel Datapath Architecture (PDA) for the planar and direct current (DC) modes of intra prediction in HEVC. PPA supports a combination of pipelining and parallel schemes, reuses the multipliers to reduce the hardware resources. PDA includes datapath0 for planar mode and datapath1 for DC mode. They function in parallel. They support all the block sizes and implemented on Artix-7 field programmable gate array (FPGA). The implemented results show that PDA uses 20% fewer resources for block size 4, while PPA uses 20%, 46%, and 62% fewer resources for block sizes 8, 16, and 32, respectively. Detailed synthesis results show that PPA and PDA achieve a throughput of 8 pixels/clock cycle and hence can support 4K videos at 30 frames per second. © 2020 IEEE.Item Complexity Analysis of Hardware Architectures for Intra Prediction unit of High Efficiency Video Coding (HEVC)(Institute of Electrical and Electronics Engineers Inc., 2020) Shastri, S.; Lakshm; I Aparna., P.High efficiency Video Coding (HEVC) is the state-of-the-art video coding technique capable of encoding Ultra High Definition (UHD) videos with better compression efficiency and has better reconstruction quality for the same bitrate as compared to its predecessors. Better compression is possible due to its complex partition and prediction methods. These benefits are at the cost of increased computational complexity, which in turn increases resource consumption and processing time. In this work, we design and implement three different architectures, viz: 1) Fully Sequential Architecture (FSA), 2) Semi-parallel Architecture (SPA) and 3) Fully Parallel Architecture (FPA), for the Intra prediction of HEVC on Field Programmable Gate Arrays (FPGA) and discuss the results. These three configurations are tested for the prediction units of sizes 4×4, 8×8 and 16×16. Results show that FSA uses nearly 70% fewer resources than FPA. Also FSA uses 51.73%, 54.33% and 52.2% less resources than SPA for 4×4, 8×8 and 16×16 block sizes, respectively. Also, the FPA implemented for all three pediction unit (PU) sizes is nearly 22 times and 5 times faster than the FSA and SPA, respectively. © 2020 IEEE.