Conference Papers

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506

Browse

Author: search.filters.author.Kumar, P.K.

Search Results

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    A semi-automatic method for carotid artery wall segmentation in MR images
    (Institute of Electrical and Electronics Engineers Inc., 2017) Kumar, P.K.; Kesavadas, C.; Rajan, J.
    The quantification of carotid artery stenosis via imaging techniques guides the physicians to take a decision regarding surgical interventions. The measurement of wall thickness from magnetic resonance (MR) images is a promising approach to measure the degree of carotid stenosis. Manual tracing of the carotid vessel walls is time consuming and is sensitive to observer variability. Further, the existing segmentation techniques are limited by the poor contrast and presence of noise in MR images. The objective this paper is to present a novel segmentation strategy for carotid lumen and outer wall from MR images. The segmentation has been carried out in two stages which starts with a user assisted region of interest selection. In the first stage, an active contour based global segmentation has been applied to classify the lumen region. In the second stage, morphological gradient of the region of interest has been computed. This is followed by particle swarm optimization based localized segmentation to separate the wall region. The results demonstrate excellent correspondence between the automatic and manual tracings for lumen and outer walls of the carotid artery. © 2016 IEEE.
  • No Thumbnail Available
    Item
    Lattice Heating Effects on Electric Field and Potential for a Silicon on Insulator (SOI) MOSFET for MIMO Applications
    (Institute of Electrical and Electronics Engineers Inc., 2023) Kumar, P.K.; Srikanth, K.; Boddukuri, N.K.; Suresh, N.; Vani, B.V.
    Finding substitutes for Silicon dioxide materials is necessary when technology is scaled back. TheSOI device conceals the self heating effects induced in the MOSFET. There exists an active path of conduction from the drain to substrate and source to substrate in the entire device to curb the heating effects. The buried oxide layer used in the device is SiO2 and it is essentially free from the issues related to fabrication and performance. The comparison is made from the bulk MOSFET and SOI MOSFET from the literature. The Silicon (Si) and Silicon Germanium (SiGe) materials are considered for the analysis. The lattice temperature effects are induced for the comparative analysis of the proposed SOI MOSFET. The main parameters of interest in the study are the electric field (lateral and vertical) and potential across the channel. © 2023 IEEE.