Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item High throughput and high capacity asynchronous pipeline using hybrid logic(Institute of Electrical and Electronics Engineers Inc., 2017) Girija Sravani, K.; Rao, R.This paper proposes a novel high throughput and high capacity asynchronous pipeline architecture, named High capacity Hybrid logic pipeline. The proposed pipeline architecture is intended for the data paths that use domino logic. This pipeline structure, combines the merits of hybrid logic encoding scheme(robustness and simplicity) and High capacity single-rail protocol (high throughput and full buffering capacity). The validity of the proposed pipeline structure has been tested by simulating a 4-bit, 10-stage FIFO in 180 nm technology. The FIFO has exhibited a throughput of 2.23 giga-items/s and this number is 23.2% higher than one of the best existing pipeline (High capacity single-rail). © 2017 IEEE.Item DDCVS Logic for Asynchronous Gate-Level Pipelined Circuits(Springer Science and Business Media Deutschland GmbH, 2021) Girija Sravani, K.; Rao, R.This paper proposes a new way of realizing the data paths for asynchronous domino logic gate-level pipeline styles. This novel approach improves the speed of the pipelines by preserving the latch-less feature of domino pipelines. In this work, the data paths of three asynchronous 16-bit adders based on APCDP, LP2/2, and HC-Hybrid pipelines are constructed using dual-rail domino cascode voltage switch (DDCVS) logic and simulated using cadence toolset in 90 nm technology. The adders based on DDCVS logic have exhibited higher performance and lower energy-delay square product compared to the adders based on domino logic. © 2021, Springer Nature Singapore Pte Ltd.