Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Estimation of attack time constant for dynamic range compressors in hearing AIDS(Institute of Electrical and Electronics Engineers Inc., 2016) Deepu, S.P.; Sumam David, S.; Ramesh Kini, M.Dynamic Range Compression (DRC) is a key component in all modern Hearing AIDS. Attack and Release time constants decide the speed with which the DRC should act to the incoming signal amplitude variation. So an accurate estimation of time constants gives a precise control over the DRC behavior. In this paper we examined various errors that occur in the output of the DRC while using conventional methods which affect attack and release time constants adversely. New methods are proposed for a better estimation of time constants in DRC. Since all the modifications are made in the estimation of attack time, there is no need to change the existing hardware for DRC. The proposed algorithm gives perfect output characteristics with zero error for test signals defined in ANSI S3.22 standards for hearing aid specifications. © 2016 IEEE.Item Area and power optimised ASIC implementation of adaptive beamformer for hearing AIDS(Institute of Electrical and Electronics Engineers Inc., 2017) Samtani, K.; Thomas, J.; Deepu, S.P.; Sumam David, S.Beamforming is a technique used in hearing AIDS to improve the intelligibility of target sound by reducing the interference from other directions. An efficient ASIC implementation of a two omnidirectional microphone array based adaptive beamforming algorithm is presented in this paper with various optimisations proposed at different stages of the hardware design. The beamform patterns and improvements in SNR values obtained from experiments conducted in a conference room environment were analysed to verify the working of the design. The architecture was implemented with 0.18 μm standard cell libraries. Cell area and power reports were analysed for different optimisations. The final area and power obtained are 0.054 mm2 and 60.54 μW respectively. © 2017 IEEE.Item FPGA implementation of adaptive beamforming in hearing aids(Institute of Electrical and Electronics Engineers Inc., 2017) Samtani, K.; Thomas, J.; Varma, G.A.; Sumam David, S.; Deepu, S.P.Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivador 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed. © 2017 IEEE.Item Wavelet based Noise Reduction Techniques for Real Time Speech Enhancement(Institute of Electrical and Electronics Engineers Inc., 2018) Ravi, B.R.; Deepu, S.P.; Ramesh Kini, M.; Sumam David, S.Fixed noise suppression techniques are generally used for speech enhancement in different low power real time systems. In this paper, we propose a modified adaptive system for classification of speech signals and noise reduction based on multi-band techniques. It involves initial identification of incoming speech segments as clean speech, speech in noise or pure noise. For the noisy speech segments, background noise classification is carried out using different wavelet-based feature sets. Noise Reduction system consists of removal of adaptive stationary noise and non-stationary noise based on classified noise type. Simulation results show that the proposed system provides optimal noise reduction and better speech quality with reduced computational complexity in adverse noisy environments. © 2018 IEEE.Item Hardware implementation of dual-tree wavelet transform based image reconstruction(Institute of Electrical and Electronics Engineers Inc., 2020) Sudhakar, H.; Kalam, L.M.; Muralitharan, S.; Deepu, S.P.; Sumam David, S.S.Real-time implementations of image processing algorithms on embedded platforms are gaining importance. In this paper, we propose an Application Specific Integrated Circuit (ASIC) architecture for the perfect reconstruction of images using wavelets with a view to extending this to denoising and feature extraction of images. An architecture that implements the Dual-Tree Wavelet Transform is presented. The architecture features a 128x128 single-port block memory and its addressing schemes, a simple upsampling/downsampling method and a folding and adding mechanism. It is implemented using 180nm technology. The results show perfect reconstruction of 128x128 grayscale images with up to 1-bit error in pixel values when compared to the corresponding input images. © 2021 IEEEItem Real-Time Hardware Implementation of 3D Sound Synthesis(Institute of Electrical and Electronics Engineers Inc., 2020) Sathwik, G.S.; Acharya, B.K.; Ali, B.; Deepu, S.P.; Sumam David, S.In this paper, hardware design and implementation to realize the effect of 3D sound with time-varying FIR filters are presented. 3D sound is a type of audio that encapsulates and recreates the effect identical to the way our ears normally experience. The spatial location of sound results in its three dimensional aspect. To synthesize it from a stereo recording, Head Related Transfer Functions (HRTFs), which describe the spectral behaviour of sounds coming from a particular direction are used. FIR filters derived from this transfer function are applied to the incoming sound, yielding spatial effect. The system was implemented using 180 nm technology libraries targeting an Application Specific Integrated Circuit (ASIC) and the functionality was validated in real-time on FPGA. © 2020 IEEE.Item Hardware Accelerator for Object Detection using Tiny YOLO-v3(Institute of Electrical and Electronics Engineers Inc., 2021) Sharma, M.; Rahul, R.; Madhusudan, S.; Deepu, S.P.; Sumam David, S.For applications that require object detection to be performed in real-time, this paper presents a custom hardware accelerator, implementing state of the art Tiny YOLO-v3 algorithm. The proposed architecture achieves a reasonable tradeoff between the speed of computation (measured in frames per second or FPS) and the hardware resources required. Each CNN layer is pipelined and parameterized to make the complete design re-configurable. The proposed hardware accelerator was synthesized using the SCL(Semi-Conductor Laboratory, India) 180 nm CMOS process and also using Vivado Xilinx software with Virtex Ultrascale+ FPGA as the target device. The pipelined architecture, along with other architectural novelties, provided a higher frame-rate of 32.1 FPS and a performance of 166.4 GOPS at 200 MHz clock frequency. © 2021 IEEE.