Conference Papers
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Item Zero delay clocking system in GHz frequency regime using CRLH metamaterial structure(2012) Soorya, K.K.; Bhat, S.M.In a multilayer structure of Integrated Circuit (IC) chips, clock signals are distributed through intermediate/global interconnects of clock tree network. These metal lines are very thin and offer high resistance and capacitive loading to the propagating electrical signals resulting in interconnect delay. This has significant impact on the propagation of clock signals, especially in GHz regime. In this work, we propose a Composite Right/Left Handed (CRLH) system augmenting the long metal interconnect line to reduce/remove the delay in the propagation of the clock signals. The CRLH system is shown to have minimum signal reflection at its resonant frequency and this feature is used for the transmission of high speed clock signals.We have designed a CRLH structure to resonate at 10 GHz. Simulation results show that when the clock signals are transmitted through interconnect-CRLH-interconnect system at this frequency, the propagation delay reduces almost to zero. © 2012 IEEE.Item A 0.5V 300μW 50MS/s 180nm 6bit Flash ADC using inverter based comparators(2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 μW. © 2012 Pillay Engineering College.Item A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.Item Switched inverter comparator based 0.5 v low power 6 bit Flash ADC(2012) Komar, R.; Bhat, S.M.; Laxminidhi, T.This paper presents an ultra low power 6 bit Flash ADC designed in 180 nm CMOS technology for ultra low power applications. The design uses inverter based comparators to reduce the silicon area and power requirement. A novel clock delaying technique is used to power on the three stages of the comparator which work in series. This reduces the power consumption and increases speed of operation. Fat tree architecture is used to design the digital encoder. The power supply used for the design is 0.5 V and the sampling rate is 50 MS/s. The design consumes ultra low power of 600 μW and spans a very small area of 0.164 mm2. In literature this is found to be the lowest for 6 bit ADCs in 180 nm with sampling frequency of 5 MS/s or above. The SNDR remains above 31.5 dB in the whole input frequency range of 0 to 25 MHz. The ADC has maximum DNL of 0.85 LSB and maximum INL of 1 LSB. The FOM of the ADC is found to be 0.39 pJ/conv. © 2012 IEEE.Item Tuned dual beam low voltage RF MEMS capacitive switches for X-band applications(2012) Shajahan, E.S.; Bhat, S.M.This paper presents a low voltage, low loss tuned RF MEMS (Radio Frequency Micro Electro Mechanical Systems) capacitive shunt switches for use in X-band. The tunable switch is designed using two shunt beams with meander springs. The switch achieved low actuation voltage along with small up state capacitance. Simulation using CoventorWare shows the actuation voltage as 7.5 Volts and up state capacitance of 47fF. HFSS simulation reveals the insertion loss in the range of (0.1-0.2) dB and up state return loss better than -25 dB in the X-band (8-12 GHz). The switch offers down state isolation of 60 dB at 12 GHz and is better than 40 dB in the frequency range 8-25 GHz. © 2012 IEEE.