Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506
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Item Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC(Institute of Electrical and Electronics Engineers Inc., 2014) Jagadish, D.N.; Bhat, M.S.A low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method achieves large savings in switching energy and reduction in total capacitance used in the capacitor array (CA) in comparison to other nonbinary capacitor array based SAR ADCs. The present technique employs two capacitor arrays that perform passive charge redistribution. The novel capacitor array architecture minimizes the parasitic influence on charge sharing process by balancing the parasitics at charge sharing nodes inside CA, and in combination with switching algorithm reduces energy consumption and area without greatly affecting the conversion time. © 2014 IEEE.Item A low-energy area-efficient dual channel SAR ADC using common capacitor array technique(Institute of Electrical and Electronics Engineers Inc., 2016) Reddy, N.S.; Jagadish, D.N.; Bhat, M.S.A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18μm CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 μW and exhibits a FOM of 101.14 fJ/conversion step. © 2016 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.