Conference Papers

Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/28506

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Author: search.filters.author.Al-Shidaifat, A.D.

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    Logic Gates Using Memristor-Aided Logic for Neuromorphic Applications
    (Springer Science and Business Media Deutschland GmbH, 2023) Khan, S.R.; Haque, M.N.; Islam, M.T.; Naik, J.D.; Al-Shidaifat, A.D.; Song, H.; Kumar, S.
    Data transfer rate has been a hornets’ nest for modern systems memory and CPU. One of the more appealing potentials to overcome the limits is to combine memory and processing at the same site where the data is stored. Memory processing has been exhibited using memristor-aided logic (MAGIC) operations in memristor. In this paper, Ag/AgInSbTe/Ta (AIST)-based memristor has been used to implement the memristor-based logic design. A memristor-only logic family referred to as MAGIC technique is used to perform logic gates such as AND, OR, NOT, and NAND. The logical operations were executed using Verilog-A model, and the figures of those operations are shown. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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    A High-Sensitive High-Input Impedance CMOS Front-End Amplifier for Neural Spike Detection
    (Springer Science and Business Media Deutschland GmbH, 2023) Naik, J.D.; Gorre, P.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.
    Neural spikes detection and monitoring for neuro-prosthetic applications require an efficient and robust front-end amplifier (FEA), which regulates the fidelity of the neural signal. This paper presents neutralization and bootstrapping techniques to overcome the input leakage currents produced by amplifiers of the input bias network. In addition, a pseudo-resistor technique ensures the FEA maintains a high-input impedance. The CMOS-based FEA architecture is executed in the advanced design system with the design kit of the CMOS process. The proposed design achieves a high-input impedance of 0.5 TΩ with a maximum simulation gain of 66.2 dB. The overall power consumption of the topology is observed as 2.6 µW with a power supply voltage of 0.9 V. The simulated noise performance of 6 nV/√Hz at 1 kHz demonstrates a high-sensitive design compared to the previous works. It is highly recommended for succeeding neuro-prosthetic applications. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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    A Low-Power Highly Efficient DC–DC Buck Converter Using PWM Technique
    (Springer Science and Business Media Deutschland GmbH, 2023) Islam, M.T.; Haque, M.N.; Khan, S.R.; Naik, J.D.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.
    Integrated digital circuits (IDCs) have become a popular option for DC–DC buck converters. This article describes a novel CMOS DC–DC buck converter architecture that leverages pulse-width modulation (PWM) for low-power technology. Double delay lines are used in the PWM power consumption which is minimized throughout design and improve unstable voltage while increasing resolution. The functioning of PWM is described using an algorithm developed. Under the working frequency of 100 kHz, the promising findings suggest that the power consumption is reduced to 1.17 W while taking up less space. With a current, the DC–DC buck converter using PWM has a high efficiency of 92.2% across a power range of 4–10 mA. Compared to traditional converters, our PWM approach reduces ripple voltage by 48% and allows in order to create within a DC–DC converter in a smaller chip area. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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    An Ultralow-Power CMOS Integrated and Fire Neuron for Neuromorphic Computing
    (Springer Science and Business Media Deutschland GmbH, 2023) Haque, M.N.; Khan, S.R.; Islam, M.T.; Naik, J.D.; Al-Shidaifat, A.D.; Kumar, S.; Song, H.
    Very large-scale integration (VLSI) implementations of spiking neurons are vital for a range of applications, from high-speed modeling of large neural systems to real-time behavioral systems and bidirectional brain-machine interfaces. The circuit solution utilized to implement the silicon neuron is determined by the application’s needs. This paper describes an ultralow-power analog circuit for realizing a leaky integrate and fire neuron model. The suggested circuit comprises parts for executing spike-frequency adaptation and modifying the neuron’s threshold voltage, in addition to being designed for low-power consumption. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.