Conference Papers
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Item A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, S.M.This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18μm technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. © 2012 IEEE.Item An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC(Institute of Electrical and Electronics Engineers Inc., 2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 μW from the power supply of 1V. © 2015 IEEE.