Journal Articles
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884
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Item Low voltage, low power chebyshev filter in 0.18 ?m cmos technology(2013) Rekha, S.; Laxminidhi, T.This paper presents an active-RC continuous time filter in 0.18 ?m standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 ?W. © 2013 World Scientific Publishing Company.Item Common mode feedback circuits for low voltage fully-differential amplifiers(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.Item Low Voltage, Low Power Gm-C filter for low frequency applications(American Scientific Publishers, 2018) Hanumantha Rao, G.; Rekha, S.This paper describes a low voltage, low power Transconductance-C (Gm-C) filter for low frequency applications. A tunable bulk-driven transconductor is proposed to realize the filter. The transcon-ductance (Gm) is tunable from 8 nS to 90 nS, which is suitable for low frequency Gm-C filters. The transconductor consumes a power of 86 nW. To evaluate the performance of the proposed transconductor, a 2nd order Butterworth low pass filter (LPF) is designed. The cutoff frequency of the filter is tunable from 74 Hz to 820 Hz. The filter offers a dynamic range of 52 dB while consuming a power of 248 nW for a nominal cutoff frequency of 456 Hz. The circuit has been designed and simulated in UMC 180 nm technology with a supply voltage of 0.5 V. © © 2018 American Scientific Publishers All rights reserved.Item Fast start crystal oscillator design with negative resistance control(Elsevier B.V., 2019) Kumar, P.; Rekha, S.Clock is an essential part of most of the integrated circuits as time base reference. It must be very accurate, highly reliable and readily available as soon as it is enabled. In all types of oscillator architectures, crystal oscillator is the most accurate and stable clock generator. But usually the crystal oscillator circuit suffers from slow startup. Therefore, it is essential to improve the startup time with optimally controlled crystal drive such that crystal drive power rating is not compromised. We propose a method that discusses about increasing the negative resistance during startup, using a startup circuit for fast start. Once the reliable startup is achieved, the negative resistance is decreased and the startup circuit is disconnected. The reduction in negative resistance is done with current steps and there are two ways in which it is achieved, the Digital control method and Analog control method. In digital control method, the current steps are timed at regular intervals and in analog control method, oscillator output amplitude is given as feedback to the startup circuit there by reducing the negative resistance. In the 32768 Hz real time clock generating oscillator, the startup time can be improved from 330 ms to 220 ms using the conventional startup method. With the proposed digital control method, lesser startup time of 160 ms is achieved and in analog control method it is further reduced to 120 ms. © 2018 Elsevier B.V.Item Ultra-low voltage, power efficient continuoustime filters in 180 nm CMOS technology(Institution of Engineering and Technology kvukmirovic@theiet.org, 2019) Rekha, S.; Vasantha, V.M.; Laxminidhi, T.The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order Gm-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the ideas. Basic building blocks are bulk driven transconductors. Gm-C filter and active-RC filter offer bandwidth of 1 MHz and 750 kHz, respectively while exhibiting a good figure of merit thus ensuring that the designs are energy efficient. Both the filters, fabricated on the same chip in 180 nm CMOS technology, operate on 0.5 V power supply. They offer a dynamic range of 45 and 46.6 dB, respectively. © The Institution of Engineering and Technology 2019.Item A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier LtdItem An area-efficient, large time-constant log-domain filter for low-frequency applications(John Wiley and Sons Ltd vgorayska@wiley.com Southern Gate Chichester, West Sussex PO19 8SQ, 2020) Hanumantha Rao, G.; Rekha, S.This paper proposes a simple technique to increase the time constant of a log-domain filter. By using the proposed technique, the capacitor value can be reduced considerably; hence, overall area of the circuit can be reduced. A second-order log-domain low-pass filter (LPF) is implemented in UMC 65-nm complementary metal-oxide semiconductor (CMOS) technology to validate the proposed technique. It occupies an area as low as 0.005 mm2 and operates with a 0.5-V supply. For a cutoff frequency of 100 Hz, the filter consumes a power of 4 nW. By adjusting the bias current, the cutoff frequency can be linearly tuned from 10 to 500 Hz. The filter has the figure of merit (FoM) of 0.68×10?13 J, which is on par with many designs listed in the literature. The filter uses the lowest capacitance/pole (0.92 pF) among the similar designs given in the literature, which shows that the present design is area efficient. © 2019 John Wiley & Sons, Ltd.Item Time Constant Enhancement Technique for Low-Frequency Filters(Birkhauser, 2020) Rao, G.H.; Rekha, S.This paper presents a simple and novel technique to enhance the time constant of a source follower (SF)-based low-pass filter (LPF) for front-end processing of biomedical signals. The proposed technique reduces the capacitor value significantly, which in turn reduces the area of the circuit. Inherent negative feedback and lower number of transistors in this circuit result in good linearity and dynamic range even with low power supply of 0.8 V. A second-order LPF of cutoff frequency (f-3dB) of 100 Hz is designed by cascading the proposed NMOS and PMOS SF LPFs. Cutoff frequency can be tuned linearly from 10 Hz to 1 kHz by varying the bias current and, hence, can be fit into the desired frequency range of different bio-potentials. The filter, designed in UMC 65 nm process, occupies an area of 0.008mm2. It offers a dynamic range of 61.85 dB while consuming a power as low as 8 nW. Figure of merit of the filter is as low as 3.23?10-14J which is better than many other filter designs reported in the literature. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.Item A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL(Birkhauser, 2020) Lad, H.; Rekha, S.; Laxminidhi, T.This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (Fmax) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 ? W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 ? m 2. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Item A Switched Capacitor-Based SAR ADC Employing a Passive Reference Charge Sharing and Charge Accumulation Technique(Birkhauser, 2020) Polineni, P.; Bhat, M.S.; Rekha, S.In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of 568?m×298?m and consumes a power as less as 0.28?W. It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/? 0.84 least significant bit (LSB) and + 0.1/? 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.