Journal Articles
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884
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Item Widely programmable high-frequency active RC filters in CMOS technology(Institute of Electrical and Electronics Engineers Inc., 2009) Laxminidhi, T.; Prasadu, V.; Pavan, S.We propose a circuit technique that enables the realization of widely programmable high-frequency active RC filters in CMOS technology. A fifth-order Chebyshev ladder filter having a digitally programmable 3-dB bandwidth (from 44 to 300 MHz) is used as a vehicle to validate our ideas. The opamp uses feedforward compensation for achieving high dc gain and wide bandwidth. The integrating resistors are realized as a series combination of a triode-operated MOSFET and a fixed polysilicon resistor. A charge-pump-based servo loop servoes the integrating resistor to a stable off-chip resistor. The principle of "constant capacitance scaling"is applied to the opamp and the integrating resistors so that the shape of the frequency response is maintained when the bandwidth is scaled over a 7 7times; range. The filter core, designed in a 0.18-?m CMOS process, consumes 54 mW from 1.8-V supply and has a dynamic range of 56.6 dB. © 2009 IEEE.Item Low power continuous time common mode sensing for common mode feedback circuits(2010) Pramod, M.; Laxminidhi, T.Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 ?m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits. © World Scientific Publishing Company.Item Low voltage, low power chebyshev filter in 0.18 ?m cmos technology(2013) Rekha, S.; Laxminidhi, T.This paper presents an active-RC continuous time filter in 0.18 ?m standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 ?W. © 2013 World Scientific Publishing Company.Item Common mode feedback circuits for low voltage fully-differential amplifiers(World Scientific Publishing Co. Pte Ltd wspc@wspc.com.sg, 2016) Rekha, S.; Laxminidhi, T.Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5V in 0.18?m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1fF to tens of femto farads. © 2016 World Scientific Publishing Company.Item 11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.Item Widely tunable low-pass gm ? C filter for biomedical applications(Institution of Engineering and Technology journals@theiet.org, 2019) Jayaram Reddy, J.R.M.; Laxminidhi, T.This study presents a fourth-order, low-pass Butterworth transconductor–capacitor gm ? C filter with tunable bandwidth for biomedical signal processing front-ends. An architecture has been proposed for realising very low transconductance values with tunability. This transconductor architecture makes it possible to realise a fully differential filter without the need for explicit common-mode feedback circuit. The filter has two tuning schemes, a resistor-based tuning (Rtuning) and a switched transconductor-based tuning (D-tuning). With R-tuning, the bandwidth is adjustable between 1 and 70 Hz and with D-tuning, the tuning range is 30 mHz–100 Hz. The filter has been designed in united microelectronics corporation (UMC) 0.18 µm complementary metal–oxide–semiconductor process. In terms of figure-of-merit, the proposed filter is found to be on par with the filters reported in the literature. © The Institution of Engineering and Technology 2018Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item Ultra-low voltage, power efficient continuoustime filters in 180 nm CMOS technology(Institution of Engineering and Technology kvukmirovic@theiet.org, 2019) Rekha, S.; Vasantha, V.M.; Laxminidhi, T.The authors propose circuit techniques to implement integrated continuous-time filters for low voltage and low power applications. A fourth order Gm-C filter and a fifth order active-RC Chebyshev filter are used as test vehicles to validate the ideas. Basic building blocks are bulk driven transconductors. Gm-C filter and active-RC filter offer bandwidth of 1 MHz and 750 kHz, respectively while exhibiting a good figure of merit thus ensuring that the designs are energy efficient. Both the filters, fabricated on the same chip in 180 nm CMOS technology, operate on 0.5 V power supply. They offer a dynamic range of 45 and 46.6 dB, respectively. © The Institution of Engineering and Technology 2019.Item 1.8 V, 25.9 nW, 91.86 dB dynamic range second-order lowpass filter tunable in the range 4-100 Hz(Institution of Engineering and Technology kvukmirovic@theiet.org, 2019) Reddy, J.R.M.K.; Laxminidhi, T.A second-order lowpass Butterworth filter with tunable bandwidth capable of offering a dynamic range of 91.86 dB operating on a supply voltage of 1.8 V is presented. The proposed filter is based on a sub-threshold source follower. The transistor bias currents are switched to enable the bandwidth tuning in the range 4-100 Hz. A proportional to absolute temperature (PTAT) current reference circuit helps to keep the bandwidth intact across process, voltage and temperature variations. The filter, designed in 0.18 ?m standard CMOS process, consumes 25.9 nW making it a potential candidate for portable biomedical applications. © The Institution of Engineering and Technology 2019.Item A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits(Taylor and Francis Ltd, 2019) Kaliyath, Y.; Laxminidhi, T.This paper presents a low-power inverter-based gain-boosted operational transconductance amplifier (OTA) for switched capacitor (SC) circuits operating at higher supply voltage (>1 V). The proposed OTA is implemented using UMC 180 nm CMOS technology with a supply voltage of 1.8 V and it offers a high dc gain with a unity gain bandwidth (UGB) suitable for audio applications. All the transistors of the proposed OTA are operated in sub-threshold region to minimize the power consumption. Gain-boosting technique is employed to achieve a higher dc gain. The post-layout simulations demonstrate the robust performance of the proposed OTA, which delivers a high dc gain of 109.3 dB and a UGB of 5.29 MHz at 81° phase margin (PM) with a capacitive load of 2.5 pF for a typical process corner at room temperature (27°C). The proposed OTA draws a quiescent current ((Formula presented.)) of 4.79 µA, resulting in a power consumption of 8.62 µW. © 2019, © 2019 IETE.