Journal Articles
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/123456789/19884
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Item Design of resolution adaptive TIQ flash ADC using AMS 0.35 ?m technology(Inderscience Publishers, 2009) Rajashekar, G.; Bhat, M.S.This paper presents a resolution adaptive flash A/D converter design and its performance. To achieve high speed, the proposed A/D converter utilises threshold inverter quantisation technique replacing conventional analogue comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analogue nodes in the ADC. The proposed ADC is a true variable resolution ADC, operates at 3-bit, 4-bit, 5-bit and 6-bit precision depending on control inputs. The proposed ADC is designed with AMS 0.35 m CMOS technology and 3.3 V power supply voltage and a prototype chip is fabricated. Simulation results and test results are presented. Copyright © 2009, Inderscience Publishers.Item Modelling of single, coupled, L and T type interconnects using state space approach(Inderscience Publishers, 2009) Soorya Krishna, K.; Pramod, M.; Bhat, M.S.In this paper, we propose models for single, coupled, L and T type on-chip global interconnect lines. Generalised models for different interconnect geometries are formed by distributed RLGC parameters using state space approach. Interconnect delay for a single interconnect line is estimated using our model and compared with other models. It is found that the error in the estimation of the delay is less in our model. Also interconnect performance metrics for the proposed models are obtained for 65 nm, 90 nm, 130nm and 180nm technology nodes based on Predictive Technology Model (PTM) values. In case of coupled, L and T section interconnects, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and can be used to characterise any interconnect structure. Further, the state matrices for any length of interconnect can be obtained by considering suitable number of rlgc segments. Copyright © 2009 Inderscience Enterprises Ltd.Item Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion(Kluwer Academic Publishers, 2014) Bini, A.A.; Bhat, M.S.Speckle is a form of multiplicative and locally correlated noise which degrades the signal-to-noise ratio (SNR) and contrast resolution of ultrasound images. This paper presents a new anisotropic level set method for despeckling low SNR, low contrast ultrasound images. The coefficient of variation, a speckle-robust edge detector is embedded in the well known geodesic "snakes" model to smooth the image level sets, while preserving and sharpening edges of a speckled image. The method achieves much better speckle suppression and edge preservation compared to the traditional anisotropic diffusion based despeckling filters. In addition, the performance of the filter is less sensitive to the speckle scale of the image and edge contrast parameter, which makes it more suitable for the detection of low contrast features in an ultrasound image. We validate the method using both synthetic and real ultrasound images and quantify the performance improvement over other state-of-the-art algorithms in terms of speckle noise reduction and edge preservation indices. © 2012 Springer Science+Business Media, LLC.Item A nonlinear level set model for image deblurring and denoising(Springer Verlag service@springer.de, 2014) Bini, A.A.; Bhat, M.S.Image deblurring and denoising are fundamental problems in the field of image processing with numerous applications. This paper presents a new nonlinear Partial Differential Equation (PDE) model based on curve evolution via level sets, for recovering images from their blurry and noisy observations. The proposed method integrates an image deconvolution process and a curve evolution based regularizing process to form a reaction-diffusion PDE. The regularization term in the proposed PDE is a combination of a diffusive image smoothing term and a reactive image enhancement term. The diffusive and reactive terms present in the model lead to effective suppression of noise with sharp restoration of image features. We present several numerical results for image restoration, with synthetic and real degradations and compare it to other state-of-the-art image restoration techniques. The experiments confirm the favorable performance of our method, both visually and in terms of Improvement in Signal-to-Noise-Ratio (ISNR) and Pratt's Figure Of Merit (FOM). © 2013 Springer-Verlag Berlin Heidelberg.Item Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices(Institute of Electrical and Electronics Engineers Inc., 2017) Somayaji, J.; Kumar, B.S.; Bhat, M.S.; Shrivastava, M.Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. © 1963-2012 IEEE.Item 11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.Item 14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.Item A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique(Springer Verlag, 2019) Polineni, S.; Bhat, M.S.; Rajan, A.A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology. © 2018, King Fahd University of Petroleum & Minerals.Item A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.Item RF Sputtered CeO2 Thin Films-Based Oxygen Sensors(Institute of Electrical and Electronics Engineers Inc., 2019) Ramshanker, N.; Lakshmi Ganapathi, K.L.; Bhat, M.S.; Mohan, S.In this paper, we report the scalable, high sensitivity, fast response, and low operating temperature Cerium oxide (CeO2) thin film-based oxygen sensors by optimizing CeO2 film thickness. CeO2 thin films of thickness ranging from 90 to 340 nm have been deposited at 400°C using radio frequency (RF) magnetron sputtering on Al2O3 substrates. Ellipsometry, X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM) have been used to characterize the CeO2 films for their thickness, structural, compositional/chemical, and surface morphology properties. Gas sensors have been fabricated using CeO2 film as a sensing material and tested in an oxygen gas environment. CeO2 film with an optimum thickness of 260 nm has shown high sensitivity (12.6) and fast response time (?10 s) along with fast recovery time (15 s) at a low operating temperature of 400°C. To the best of our knowledge, these are the best values reported till date for undoped CeO2 thin film-based oxygen sensors. Furthermore, from the sensor's response, it was observed that there was no drifting from the baseline. This superior performance of CeO2 thin film-based oxygen sensor may be attributed to the combination of three factors, i.e., 1) high surface energy and reactivity due to the presence of (200) oriented CeO2 plane; 2) low resistance due to better crystallinity; and 3) perfect stoichiometry with required roughness. © 2001-2012 IEEE.