2. Conference Papers
Permanent URI for this collectionhttps://idr.nitk.ac.in/handle/1/7
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Item Real-Time Hardware Implementation of 3D Sound Synthesis(2020) Sathwik G.S.; Acharya B.K.; Ali B.; Deepu S.P.; David S.In this paper, hardware design and implementation to realize the effect of 3D sound with time-varying FIR filters are presented. 3D sound is a type of audio that encapsulates and recreates the effect identical to the way our ears normally experience. The spatial location of sound results in its three dimensional aspect. To synthesize it from a stereo recording, Head Related Transfer Functions (HRTFs), which describe the spectral behaviour of sounds coming from a particular direction are used. FIR filters derived from this transfer function are applied to the incoming sound, yielding spatial effect. The system was implemented using 180 nm technology libraries targeting an Application Specific Integrated Circuit (ASIC) and the functionality was validated in real-time on FPGA. © 2020 IEEE.Item Pipelined Parallel Processor to implement MD4 Message digest algorithm on Xilinx FPGA(1998) David S.The paper presents a pipelined parallel processor architecture design to implement the MD4 message digest algorithm which computes the message digest or the fingerprint of 128 bit fixed length, for any arbitrary length of input message. The processor implements the arithmetic, logic and circular shift operations by a pipelined parallel process. The architecture is designed to suit the design flexibility of the Xilinx Field Programmable Gate Arrays (FPGAs) The processor reads the message from an external RAM, 16-bit at a time and internal operations are performed with 32-bit data. The major advantage of the design is increased speed of computation and minimum hardware. The processor computes the digest with a speed approximately three times faster than the software version implemented in DSP processors.