2. Conference Papers

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A 0.5 V, 1 nA Switched Capacitor PTAT Current Reference Circuit
(2019) Hanumantha, Rao, G.; Rekha, S.
This paper presents a low voltage, low power Proportional to Absolute Temperature (PTAT) current reference circuit. Switched capacitor is used instead of a large resistor, which in turn reduces the area of the circuit and makes the circuit less process sensitive. The proposed circuit has been designed using UMC 65 nm CMOS technology and simulated in Cadence Virtuoso. It generates a reference current (Iref) of 1 nA at 0.5 V supply voltage (Vdd) at room temperature (27�C) and follows PTAT characteristics in the temperature range of -10�C to 80�C. The total power consumption of the circuit is as low as 1.5 nW. The supply voltage sensitivity of Iref is 2.7 %/V, which shows that the proposed circuit is less sensitive to supply voltage variations. Index Terms - Low voltage, Low power, PTAT current, Switched capacitor. � 2019 IEEE.
A 0.5 V, 20 ?w pseudo differential 500 kHz Gm-C low pass filter in 0.18 ?m CMOS technology
(2012) Harishchandra, V.M.; Laxminidhi, T.
Scaling of supply voltage due to shrinking in the device sizes has lead to bulk driven circuit techniques specially for analog circuits that operate at low supply voltages. In this paper we present a bulk driven pseudo differential low power, continuous time Cochlea 2 nd order Butterworth low pass filter operating at a supply voltage of 0.5 V. The filter uses Gm-C technique in 0.18 ?m n-well standard CMOS process and has a bandwidth of 500 kHz. Simulations results have shown that the filter offers a dynamic range of 48 dB while consuming a power of 20 ?W. Simulated Figure of Merit (FOM) is found to be 0.52 fJ and is found to be the lowest among similar low voltage filters found in literature. The percentage change in transconductance is less than ?5% for temperature variation of 0-70�C at 0.5 V supply voltage and across five process corners. � 2012 IEEE.
0.5 V, 36?W Gm-C butterworth low pass filter in 0.18?m CMOS process
(2012) Harishchandra, V.M.; Laxminidhi, T.
This paper presents a low voltage, low power continuous-time (G m-C) 4th order low pass Butterworth filter with a 3-dB bandwidth of 1MHz and capable of operating at supply voltage as low as 0.5V in 0.18 ?m. The filter uses bulk-driven technique for achieving the necessary head-room. The simulation results show that the filter has a peak-to-peak signal swing of 1.2V (differential) for 1% THD and a dynamic range of 54 dB. The power consumed by the filter is 36?W when operating at a voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ and is found to be lowest among the similar filters found in the literature. � 2012 IEEE.
0.5 V, low power, 1 MHz low pass filter in 0.18 ?m CMOS process
(2012) Vasantha, M.H.; Laxminidhi, T.
In this paper a low power continuous-time 4th order low pass Butterworth filter operating at power supply of 0.5 V is presented. A 3-dB bandwidth of 1 MHz using technology node of 0.18 ?m is achieved. In order to achievenecessary head-room, the filter uses pseudo-differential bulk-driven transconductor. A master-slave based common modefeedback(CMFB) circuit sets the output common mode voltageof transconductor. The simulation results show that the filter has a dynamic range of 54 dB and consumes a total power of 36 ?W when operating at a supply voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ, lowest among similar low-voltage filters found in the literature. The simulation result show that the 3-dB bandwidth variation for process, voltage and temperature is less than �10%. � 2012 IEEE.
A 0.5V 300?W 50MS/s 180nm 6bit Flash ADC using inverter based comparators
(2012) Komar, R.; Bhat, M.S.; Laxminidhi, T.
This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 ?W. � 2012 Pillay Engineering College.
A 0.8 V, 5 nA PTAT current reference circuit with improved supply voltage sensitivity
(2019) Hanumantha Rao G.; Muhammed Mansoor C.B.; Rekha S.
This paper presents a low voltage, low power Proportional to Absolute Temperature (PTAT) current reference circuit with improved supply voltage sensitivity. The proposed circuit is designed and laid out in UMC 65 nm CMOS technology and simulated using Cadence Virtuoso. It generates a reference current (Iref) of 5 nA at 0.8 V supply voltage (Vdd) at room temperature (27°C). Composite transistors are used to improve the supply voltage sensitivity when compared to a traditional beta-multiplier circuit. The current reference circuit consumes a power of 8 nW and follows PTAT characteristics in the temperature range of 0°C to 80°C. The supply voltage sensitivity of Iref is 2.6 %/V, which shows that the proposed circuit is less sensitive to supply voltage variations. © 2019 IEEE.
A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
(2013) Lad, K.; Bhat, M.S.
A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. � 2013 IEEE.
1.5�C accurate CMOS temperature sensor with a single point trim at 85�C
(2016) Hareesh, P.K.; Laxmindhi, T.
This paper presents a temperature sensor with an accuracy of 1.5�C. The paper analyzes inaccuracy of the existing temperature sensors and outlines the techinques to overcome them. The sensor is based on a CMOS current reference which is almost constant over process/corner and voltage variation. Most of the techniques known today for generating a process and voltage independent current source have very stringent constraints on sizing of the transistors. The current source proposed in the paper relaxes such constraints thus easing the portability across various technology nodes. The sensor designed in TSMC 28 nm CMOS process offers the accuracy of 1.5�C over a temperature range of-40�C to 125�C with a single point trim at 85�C. The sensor consumes a power of 90 ?W of power when operating on 1.8 V supply. � 2016 IEEE.
A 1.8 v 11.02 ?w single-ended inverter-based OTA with 113.62 dB gain
(2016) Kaliyath, Y.; Laxminidhi, T.
This paper presents a low power 1.8 V single-ended operational trans conductance amplifier (OTA) with a very high dc gain targeted for audio applications. Cascoding and gain boosting are employed to achieve the high gain. The amplifier is implemented in UMC 180 nm CMOS technology. For a typical process corner, the amplifier provides a dc gain of 113.62 dB and a unity gain bandwidth of 2.49 MHz at 62.9� phase margin with capacitive load of 2.5 pF. The amplifier consumes only 6.12 ?A of quiescent current from 1.8 V supply. The amplifier exhibits good performance across all the process corners with the use of body bias technique. � 2016 IEEE.
(2,1)-Lagged fibonacci generators using elliptic curves over finite fields
(2009) Shankar, B.R.; Karuna, Kamath, K.
A novel pseudorandom sequence generator is presented in this paper. The genesis of this new generator is evolved from the concept of Lagged Fibonacci generator[1] applied to points on elliptic curves over a finite field. It is observed that the generator has a long period. Also a successful statistical testing of the randomness attributes of the given generator, in accordance with the National Institute of Standards and Technology test suite, admits to a key stream source that is in conformance with the Advanced Encryption Standard for data encryption. � 2009 IEEE.
2019-nCoV disease control and rehabilitation: Insights from twitter analytics
(2020) Chetty N.; Alathur S.; Kumar V.
Coronaviruses are the large family of viruses and life threatening with the capabilities to cause respiratory related diseases. The current outbreak of 2019-nCoV (novel Coronavirus) is challenging governance authorities and health care systems around the globe. The epidemic of 2019-nCoV is affecting people globally. The purpose of this paper is to examine the current status of disease control and rehabilitation in relation to outbreak of 2019-nCoV. In this regard, the Twitter social media contents are collected, analyzed and interpreted. Using a set of appropriate keywords, 110000 tweets are extracted from Twitter social media. The collected tweets are first pre-processed and then analyzed with a software developed in R language. The discussions on social media in relation to the outbreak of 2019-nCoV involves disease control, rehabilitation and anti-rehabilitation. Expressions involving specific locations revealed that the discussions are more oriented towards antirehabilitation than rehabilitation and disease control. The content analysis also revealed that the outbreak epidemic victimizes those who possess weaker immune system. © 2020 IEEE.
A 28-32GHz CMOS LNA with broadband approach for 5G Mm-wave communication cells
(2019) Vignesh R.; Gorre P.; Kumar S.; Song H.
This paper first time reports a wideband low noise amplifier (LNA) with achievable minimum atmospheric absorption frequency band for 5G millimeter wave communication cells. A novel suspended substrate line based parallel-series network is optimized and analyzed that demonstrates a wideband response. The proposed LNA consists of two stage Cascode topology with incorporated parallel-series network and microwave components that provides broadband ranging from 28GHz to 32GHz. A full of two stage Cascode LNA overcoming the traditional mismatching constraints with consideration of suspended substrate lines (SSL) and Tee-junction in the proposed design. It is observed that suspended lines reduce parasitic and bulk effects of devices and enables LNA to provide broadband communication for 5G macro and micro cells. The proposed design is realized using RF 65nm Magna Hynix CMOS process with layout cell. The simulation results reveals that 28GHz-32GHz wide band with maximum forward gain of 25dB. The minimum noise figure of 2.5dB is achieved with optimization of passive components. The input impedance (real and imaginary) and smith chart realization for LNA provides satisfactory performance. © 2019 IEEE.
3-D radar imaging using extended 2-D range migration technique
(2018) Nagarad, S.R.; Sourabh, A.S.; Shripathi, Acharya U.; Srihari, P.; Prasad, S.; Rao, P.H.
A three dimensional (3-D) imaging system is implemented by employing 2-D range migration algorithm (RMA) for frequency modulated continuous wave synthetic aperture radar (FMCW-SAR). The backscattered data of a 1-D synthetic aperture at specific altitudes are coherently integrated to form 2-D images. These 2-D images at different altitudes are stitched vertically to form a 3-D image. Numerical simulation for near-field scenario are also presented to validate the proposed algorithm. � 2017 IEEE.
3-Dimensional numerical study of cooling performance of a heat sink with air-water flow through mini-channel
(2016) Majumder, S.; Majumder, A.; Bhaumik, S.
The present microelectronics market demands devices with high power dissipation capabilities having enhanced cooling per unit area. The drive for miniaturizing the devices to even micro level dimensions is shooting up the applied heat flux on such devices, resulting in complexity in heat transfer and cooling management. In this paper, a method of CPU processor cooling is introduced where active and passive cooling techniques are incorporated simultaneously. A heat sink consisting of fins is designed, where water flows internally through the mini-channel fins and air flows externally. Three dimensional numerical simulations are performed for large set of Reynolds number in laminar region using finite volume method for both developing flows. The dimensions of mini-channel fins are varied for several aspect ratios such as 1, 1.33, 2 and 4. Constant temperature (T) boundary condition is applied at heat sink base. Channel fluid temperature, pressure drop are analyzed to obtain best cooling option in the present study. It has been observed that as the aspect ratio of the channel decreases Nusselt number decreases while pressure drop increases. However, Nusselt number increases with increase in Reynolds number. � 2016 Author(s).
A 36-Pulse AC-DC Converter with DC Side Tapped Interphase Bridge Rectifier for Power Quality Improvement
(2018) Saravana, Prakash, P.; Kalpana, R.; Chethana, K.S.; Singh, B.
This paper presents a circuit configuration to reduce the harmonic contents at the AC mains of a 12-pulse zigzag configured autotransformer based DBR. The proposed circuit configuration employs a tapped interphase bridge rectifier at the DC side of 12-pulse DBR that results in higher pulses in the supply current. Thus, reducing the harmonic content and thereby improving the power quality of the system. Since the autotransformer employed is zigzag configured, the need for ZSBT is eliminated. Moreover, the proposed circuit configuration at the DC side shapes the supply current near to a sine wave. Further, the proposed configuration is analyzed, simulated in MATLAB Simulink and the simulation results are presented, which confirms the improvement in power quality parameters in the input AC line current. Further, the viability of the proposed configuration is verified by experimental results which confirm the suitability of the proposed configuration in AC-DC applications. � 2018 IEEE.
3D Estimation and visualization of motion in a multicamera network for sports
(2011) Kumar, A.; Chavan, P.S.; Sharatchandra, V.K.; Sumam, David S.; Kelly, P.; O'Connor, N.E.
In this work, we develop image processing and computer vision techniques for visually tracking a tennis ball, in 3D, on a court instrumented with multiple low-cost IP cameras. The technique first obtains 2D ball tracking data from each camera view using 2D object tracking methods. Next, an automatic feature-based video synchronization method is applied. This technique uses the extracted 2D ball information from two or more camera views, plus camera calibration information. In order to find 3D trajectory, the temporal 3D locations of the ball is estimated using triangulation of correspondent 2D locations obtained from automatically synchronized videos. Furthermore, in order to improve the continuity of the tracked 3D ball during times when no two cameras have overlapping views of the ball location, we incorporate a physics-based trajectory model into the system. The resultant 3D ball tracks are then visualized in a virtual 3D graphical environment. Finally, we quantify the accuracy of our system in terms of reprojection error. � 2011 IEEE.
3D face reconstruction using frontal and profile views
(2013) Narayana, S.; Rohit; Rajagopal; Rakshith; Antony, J.
We present a methodical approach for 3-D face reconstruction. Two orthogonal images, the frontal and profile views of the face, are used with a constructed generic model to obtain the 3-D face model. The need for 3-D face modelling has been growing due to its application in biometrics, forensic, animation, gaming etc. Face localization in the image is performed using fast skin colour detection technique. Feature points from the face images are identified and extracted. Global deformation and local deformation techniques are applied to deform the 3-D generic face model constructed using the feature points extracted, to obtain the 3-D face model. The 3D model of the face reconstructed will be of high accuracy and high clarity. � 2013 IEEE.
3D printable modules for manually reconfigurable manipulator with desired D-H parameters
(2020) Marebal, D.; Guruprasad, K.R.
Modular robots are designed to increase the utilization of robots by modularizing their architecture. We discuss manually reconfigurable manipulators, where a manipulator of desired kinematic configuration is built by assembling the available modules. In the case of a serial-link manipulator with revolute joints, the joint angle is a variable. Out of the remaining three D-H parameters, namely, link-length, link-offset and link-twist, the twist angle influences the workspace the most. This work proposes a conceptual design and fabrication of individual modules which can be assembled to obtain a modular manipulator with desired kinematic configuration in terms of twist angles between any two consecutive joints. We also discuss possible provisions for length adjustment of a link. Designed modules are fabricated using 3D printer. As we focus on manually reconfigurable manipulators, simplicity of individual modules, in terms design, fabrication, and assembly, has been given higher priority, in contrast to similar designs available in the literature. � 2020, Springer Nature Singapore Pte Ltd.
3D Printing & Mechanical Characteristion of Polylactic Acid and Bronze Filled Polylactic Acid Components
(2018) Aveen, K.P.; Vishwanath, Bhajathari, F.; Jambagi, S.C.
Rapid prototyping (RP) technologies have emerged as fabrication methods to obtain engineering components within a short span of time. Desktop 3D printing, also referred as Additive Manufacturing (AM) technology is a powerful method of rapid prototyping technique that can fabricate three-dimensional engineering components. Poly Lactic acid (PLA) is a green alternative to petrochemical commodity plastics, used in packaging, agricultural products, disposable materials, textiles, and automotive composites, 3-D printing technology enables fabrication of PLA and bronze filled PLA, which has less tensile and flexural modulus. In order for 3D printed parts to be useful for engineering applications, the mechanical properties of the material will play an important role in the functioning of the components. In the present study, commercial grade PLA & bronze filled PLA has been considered as material for preparation of samples using desktop 3D printer. The samples were tested for their mechanical characteristics like Tensile and flexural strength properties. The test Samples were fabricated using 3D printing with different layer height and with different layer build-up speed. Comparison between the PLA & bronze filled PLA based on the experimental results are discussed and found PLA has superior tensile and flexural property when compared to Bronze filled PLA. � Published under licence by IOP Publishing Ltd.
A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC
(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.
This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18?m technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. � 2012 IEEE.