Browsing by Author "Vinaya, S.J."

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    Impact of Gate Oxide Thickness Variation on the On-state Safe Operating Area and FoM of SOI-Junctionless FinFET considering the Self-heating Effects
    (Institute of Electrical and Electronics Engineers Inc., 2024) Vinaya, S.J.; Nikhil, K.S.
    A 3D Silicon On Insulator-Junctionless FinFET (SOI-JLFinFET) device structure has been simulated to explore the impact of gate oxide thickness (tox) variation on performance metrics such as breakdown voltage, maximum drain current, and the safe operating area (SOA). To analyze the SOA thoroughly, simulations are done for SOI-JLFinFET with oxide thicknesses ranging from 2 nm to 5 nm. The effect of tox on the peak temperature of SOI-JLFinFET is also studied. The distribution of the electric field vector in the channel region has been examined for both thin and thick gate oxides. The device's performance for amplification application has also been assessed by obtaining the transconductance (gm) at different drain voltages. Furthermore, the overall effect of gate oxide thickness (tox) variation on the on-state breakdown voltage (Vbr,ON) and maximum drain current(ID,max), which impact the device's power handling capability and Figure of Merit (FoM) have been studied. © 2024 IEEE.
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    Investigation of the impact of gate oxide thickness variation of Junction-less FinFET using BSIM-CMG model for LIF neuron and STDP circuit application
    (Institute of Physics, 2025) Vinaya, S.J.; Rao, R.; Nikhil, K.S.
    In neuromorphic circuits, Leaky Integrate-and-Fire (LIF) neuron and Spike-Timing-Dependent Plasticity (STDP) circuits are very much essential. These circuits are significantly influenced by the characteristics of the transistors used in their design. In this work, the impact of gate oxide thickness variation on the performance of FinFET-based neuromorphic circuits using the (Berkeley Short-channel IGFET Model—Common Multi-Gate) BSIM-CMG model is investigated. TCAD simulations are carried out to analyze the electrical characteristics of FinFETs with varying oxide thicknesses. The circuit-level simulations are carried out using Cadence tool to evaluate their impact on synaptic weight updates in STDP and LIF neuron operation and circuits. The results show that reducing the gate oxide thickness from 5 nm to 2 nm enhances the capacitor voltage response, thereby improving charge storage and synaptic weight modulation. It has been shown that there is a consistent increase in capacitor voltage as oxide thickness decreases, which directly impacts the learning efficiency of STDP circuits. Varying oxide thickness will also impact on firing frequency of LIF neuron circuit.These results signifies performances of STDP and LIF neuron circuits for neuromorphic applications. © 2025 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.