Browsing by Author "Prashantha Kumar, H."

Now showing 1 - 11 of 11

A 280?W high gain inductively degenerated LNA for medical radio communication
(Serials Publications serialspublications@vsnl.net, 2016) Vasudeva Reddy, K.; Girija Sravani, K.; Prashantha Kumar, H.
An ultra-low power, high gain inductively degenerated common source (IDCS) LNA for medical radio (MedRadio) communications in the frequency band of 401-406 MHz is implemented using 0.18-?m technology. An upsurge LNA is designed for biomedical applications with an emphasis on the covenant between gain, noise and power consumption. The IDCS LNA operates in subthreshold region which extremely reduces the power consumption and relaxes the voltage headroom without screwing the LNA performance. The relaxed voltage headroom concedes current-reuse technique to implement single to differential (SD) LNA or to stack mixer on top of LNA. The proposed LNA achieves power gain (S21) of 21 dB, S11 & S22 are much less than -10 dB, NF of 2.1 dB and P1dB of -18 dBm while consuming 280 ?A current from a 1-V supply voltage. The overall pre and post layout simulations of proposed LNA shows acceptable agreement with theoretical predictions. The layout occupying 0.587 mm2. The gain enhancement and reduction in power has been optimized compared with previous works implies that LNA obtains the highest figure of merit. © 2016 International Science Press.
A novel 5.1–7.1 GHz front-end power amplifier for wireless applications with ?35 dB Error Vector Magnitude
(Elsevier Ltd, 2024) Pawankumar, B.; Prashantha Kumar, H.
A Power Amplifier (PA) is proposed for WiFi-6E applications, specifically designed to support WLAN 802.11ax standard to achieve significant linear power. The proposed PA is designed to operate in the entire 5 GHz and 6 GHz frequency bands. The design involves a two-stage configuration, initial stage adopts a linear driver, while the subsequent amplification stage is structured as a differential cascode. UMC 65 nm CMOS process technology is used to design a PA in commercial Cadence platform. The layout occupies core area of 0.24 mm2. Proposed PA delivers a power gain of 20 dB, Power Added Efficiency (PAE) of 19% and 1 dB compression point (P1dB) is of 24.5 dB is achieved for continuous wave (CW) signal. For the 802.11ax source, the recorded average power output (Pavg) is 17.1 dBm at an Error Vector Magnitude (EVM) ??35 dB, across the 5–7 GHz. The PA delivers Pavg of 10 dBm at worst corner case in PVT variation analysis. While the majority of recent works in WLAN PA confines the investigation to 5 GHz band, this paper broadens the scope by extending the study by up to 7.050 GHz in 6 GHz band. The incorporation of 6GHz band enables WiFi-6E to utilize up to 1,200 MHz of unencumbered spectrum, significantly enhancing the available bandwidth relative to earlier WiFi standards. The increased bandwidth facilitates high data rate applications, such as streaming and gaming. © 2024 The Authors
A Wi-Fi 6E Tri-Band Power Amplifier for WLAN Applications Featuring a Novel Re-configurable Matching Network
(Birkhauser, 2025) Pawankumar, B.; Prashantha Kumar, H.
This article introduces a novel design methodology of a re-configurable tri-band matching network along with Power Amplifier (PA) that supports the latest WLAN applications. The implemented matching network/circuit, specifically designed for the 2.4 GHz band, enables amplifier to achieve a linear power exceeding 11 dBm. Incorporating the proposed matching circuit, standalone PA is designed to support tri-band operation (2.4 GHz, 5 GHz, and 6 GHz) for the emerging wireless local area network (WLAN) applications. These designs are realized using UMC 65 nm CMOS technology in commercial Cadence Virtuoso design environment with a core area occupying 0.33 mm2. In the 2.4/5/6-GHz WLAN bands, the power amplifier achieves a output power 1-dB compression (P1dB) point ranging from 20.3 to 22.4 dBm, with power-added efficiency (PAE) values ranging from 10 to 16%. The power amplifier delivers an average power output (Pavg) of 11.6–14.5 dBm with an Error Vector Magnitude (EVM) of ? 35 dB for 80-MHz bandwidth WLAN 802.11ax source, with source EVM maintained at ? 50 dB. The standalone PA and novel matching circuit for 2.4 GHz presents one of the first published designs in the literature for tri-band WLAN applications. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2024.
Adaptive receive-antenna selection technique for Spatial Modulation MIMO systems
(Institute of Electrical and Electronics Engineers Inc., 2015) Neha, N.; Koila, S.; Prashantha Kumar, H.; Sripati, U.
In this paper, we propose an adaptive receive antenna selection technique for Spatial Modulation (SM) MIMO systems. The proposed method is simple and uses channel state information (CSI) available at the receiver to choose the best subset of active receive antennas among the available Nr receive antennas. Simulation results show that SM MIMO system with the proposed receive antenna selection scheme provides a performance gain of approximately 5 dB over conventional SM system (SM MIMO system without antenna selection). The proposed scheme does not increase the RF chain requirement at the receiver and retains all the benefits of SM MIMO. Â© 2015 IEEE.
Design and construction of BCH codes for enhancing data integrity in multi level flash memories
(Inderscience Publishers, 2012) Rajesh Shetty, K.; Ramakrishna, K.; Prashantha Kumar, H.; Sripati, U.
Flash memories have found extensive application for use in storage devices. The storage capacity and reliability of these devices have increased enormously over the years. With increase in density of data storage, the raw bit error rate (RBER), associated with the storage device increases. Error control coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes for flash memories based on multi level cell (MLC) concept. This is in continuation of our work on synthesis of BCH codes for improving the performance of flash memories based on single level cells (SLC). The improvement in device integrity resulting from the use of these codes has been quantified in this paper along with computation of parameters which allows modelling of flash memory as an equivalent channel. While synthesising codes, we have adhered to the limitations imposed by the memory architecture. Use of these codes in storage devices will result in considerable enhancement of device reliability and consequently open up many new applications for this class of storage devices. © 2012 Inderscience Enterprises Ltd.
Inductor-less PVT robust gain switching balun LNA for multistandard applications
(Taylor and Francis Ltd. michael.wagreich@univie.ac.at, 2019) Vasudeva Reddy, K.; Prashantha Kumar, H.
An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g m is not more than 10%. The proposed LNA is implemented in UMC 0.18-?m RF CMOS technology. The core area is 182 ?m × 181 ?m. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3? deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations. © 2019, © 2019 Informa UK Limited, trading as Taylor & Francis Group.
Power Amplifier for front-end WiFi-6E application
(Institute of Electrical and Electronics Engineers Inc., 2024) Pawankumar, B.; Prashantha Kumar, H.
This paper proposes a dual-band Power Amplifier (PA) suited to WLAN 802.11ax applications in wireless communication. Operating in frequency range of 5GHz to 7GHz, the PA employs a single-transistor design biased in a class-AB configuration. Implemented using UMC 65nm CMOS PDK, the compact layout inclusive of pad frames occupies an area of 880Âµm Ã—418Âµm (0.37mm2). For continuous wave (CW) source, post-layout simulation offers a gain of 11.2dB, output saturated power of 20.8dB and a Power Added Efficiency (PAE) of 20.8%. For 802.11ax MCS-11 signals, linear power output (Pavg) exceeds 12dBm at Error Vector Magnitude (EVM) =-35dB across the 5GHz and 6GHz bands. Unlike most literature that predominantly focuses on WLAN PA studies up to 6GHz, this paper extends the investigation up to 7.050GHz suitable for WiFi-6E application. Â© 2024 IEEE.
Soft decision decoding of Davydov-Tombak codes using a parity check tree
(2010) Prashantha Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Shankarananda, B.
Davydov and Tombak have designed an excellent single error correction-double error detection (SEC-DED) code that appears to be more capable of detecting triple and quadruple errors than the conventional Hamming SEC-DED codes. These codes have been applied to memory subsystems and digital storage devices in order to achieve efficient and reliable data processing and storage. A new approach to soft decision decoding of Davydov-Tombak codes using a parity check tree associated with the Tanner graph is presented. For the AWGN channel, gains in excess of 1.6dB at reasonable bit error rates with respect to conventional hard decision decoding are demonstrated for the (40, 33), (37, 30), (35, 28) and (72, 64) Davydov-Tombak codes. Â©2010 IEEE.
Soft decision Fano decoding of block codes over discrete memoryless channel using tree diagram
(2012) Prashantha Kumar, H.; Sripati, U.; Rajesh Shetty, K.; Setty Shankarananda, B.
A novel low complexity soft decision technique which allows the decoding of block codes with tree structure is proposed. These codes are shown to have a convenient tree structure that allows Fano decoding techniques to be used to decode them. The Fano algorithm searches through the tree structure of the block code for a path which has the optimal value of the Fano metric function. When a new candidate codeword is found, an optimality check is performed on it by using the threshold. If checked successfully, the candidate codeword is the most likely codeword and the search stops. The basic idea of this approach is to achieve a good error performance progressively in a minimum number of steps. For each decoding step, the error performance is tightly bounded and the decoding is terminated at the stage where either optimum or near optimum error performance is achieved. As a result, more flexibility in the trade off between performance and decoding complexity is provided. Some examples of the tree construction and the soft decision Fano decoding procedure are discussed. © 2012 FEI STU.
Synthesis of BCH codes for enhancing data integrity in flash memories
(2010) Rajesh Shetty, K.; Sripati, U.; Prashantha Kumar, H.; Shankarananda, B.
Flash memories have found extensive application for use in portable storage devices. They have been used for code storage as well as data storage. The storage density associated with these devices has increased tremendously in the past few years. This has necessitated very dense packing of data bits on the device. This gives rise to increased Raw Bit Error Rate (RBER) as a result of Inter Symbol Interference (ISI) between bits stored in adjacent cells. This necessitates the use of powerful error control codes to guarantee information integrity. With the increase in density of data storage, the raw bit error rate (RBER) associated with the storage device increases. Error Control Coding (ECC) can be used to reduce the RBER to acceptable values so that these devices can be employed to store information in applications where data corruption is unacceptable. In this paper, we describe the synthesis of BCH codes based on memory models proposed by the semiconductor industry. These codes have better error correcting capability than the codes used in current practice. Â©2010 IEEE.
Target Estimation Performance Improvement in Cooperative Radar and Communication system Spectrum Sharing
(Institute of Electrical and Electronics Engineers Inc., 2021) Gunnery, S.; Pardhasaradhi, B.; Prashantha Kumar, H.; Srihari, P.
This paper presents target estimation performance improvement in cooperative radar and communication system spectrum sharing system model. Due to cooperation, target returns results from the communication transmitter are also exploited to improve the target estimation performance. Further, Cramer-Rao Lower Bound (CRLB) is considered as a metric to evaluate the target estimation performance. In addition, the effect of transmitting energy and target reflection coefficient on CRLB is analyzed. The cooperative system model is compared with the non-cooperative radar and communication system spectrum sharing operation and stand-alone radar system operation. Results show that the cooperative radar and communication system spectrum sharing system model provides improved performance compared to non-cooperative and stand-alone operations. Â© 2021 IEEE.