Browsing by Author "Praharshita, D.S.L."

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    DSP Architectures of Covariance Intersection Fusion Algorithm for Automotive Sensor Fusion
    (Institute of Electrical and Electronics Engineers Inc., 2023) Praharshita, D.S.L.; Achala, G.; Srihari, P.; Shripathi Acharya, U.S.; Pardhasaradhi, B.
    The data fusion from sensors within the automotive vehicle is vital for improved accuracy and safety. The centralized and information matrix fusion (IMF) algorithms are famous for providing an optimal fusion estimate. However, the IMF is not viable in automotive sensor fusion applications due to the limited bandwidth and low hardware resources. Hence, distributed fusion technology is widely adopted in the automotive sensor applications to achieve high-speed and low-area realizations. This paper proposes three digital signal processing (DSP) architectures for covariance intersection (CI) fusion algorithm: Pipelined-traditional CI, adder-ladder CI, and pipelined adder-ladder CI. The proposed DSP architectures are evaluated with hardware resource consumption (multipliers, adders, and delays), maximum achievable frequency, and latency of the architecture. In addition, proposed CI algorithms for Digital Signal Processing (DSP) architectures are compared with IMF DSP architectures. The hardware resources and optimal pipeline stages required for CI with respect to N number of sensors are provided. The traditional pipeline algorithm requires N number of stages where as the proposed pipelined version of adder-ladder CI requires a N-1 pipeline stage with additional 7N-1 and 7N-3 delay elements for even and odd number of sensors to achieve the overall system operating frequency to an operation of multiplier. The proposed DSP architectures are suitable for automotive sensor fusion due to their high operating frequency and low hardware resources. © 2023 IEEE.
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    High-Frequency and Low-Latency DSP Architecture for Information Matrix Fusion
    (Institute of Electrical and Electronics Engineers Inc., 2021) Praharshita, D.S.L.; Pardhasaradhi, B.; Srihari, P.; Shripathi Acharya, U.S.; Sharma, G.V.K.
    The centralized fusion architecture gives optimal global estimate by fusing all the measurements pertaining to a given target. The centralized architectures are computationally huge and requires full data rate requirements. Hence, in practice, decentralized architectures with Information matrix fusion (IMF) is popular to derive an estimate which is equal to optimal global estimate accomplished in centralized architecture. In this paper, a digital signal processing (DSP) architectural minimization technique of pipelining is applied to derive the highspeed IMF. We proposed two different DSP architectures, namely pipelined traditional IMF and pipelined adder-ladder IMF to reduce the critical path, which inturn, increases the architecture's operating frequency. Further, we derived an optimal number of pipeline stages and hardware resources that are required for a generalized N sensors case. The proposed pipelined adder-ladder IMF configuration requires a N + 1 pipeline stage and N + 2 pipeline stages for an even number of sensors and an odd number of sensors respectively. Besides that, The pipelined traditional IMF requires 2N + 1 stages to optimally pipeline and achieve the same operating frequency as that of pipelined adder-ladder IMF. Furthermore, the proposed pipelined adder-ladder IMF is superior in performance (less hardware and less latency) compared to pipelined traditional IMF. The theoretical analysis is performed with metrics (critical path, number of resources, and maximum achievable frequency) to compare various architectures presented in this research work. © 2021 IEEE.