High-Frequency and Low-Latency DSP Architecture for Information Matrix Fusion

Abstract

The centralized fusion architecture gives optimal global estimate by fusing all the measurements pertaining to a given target. The centralized architectures are computationally huge and requires full data rate requirements. Hence, in practice, decentralized architectures with Information matrix fusion (IMF) is popular to derive an estimate which is equal to optimal global estimate accomplished in centralized architecture. In this paper, a digital signal processing (DSP) architectural minimization technique of pipelining is applied to derive the highspeed IMF. We proposed two different DSP architectures, namely pipelined traditional IMF and pipelined adder-ladder IMF to reduce the critical path, which inturn, increases the architecture's operating frequency. Further, we derived an optimal number of pipeline stages and hardware resources that are required for a generalized N sensors case. The proposed pipelined adder-ladder IMF configuration requires a N + 1 pipeline stage and N + 2 pipeline stages for an even number of sensors and an odd number of sensors respectively. Besides that, The pipelined traditional IMF requires 2N + 1 stages to optimally pipeline and achieve the same operating frequency as that of pipelined adder-ladder IMF. Furthermore, the proposed pipelined adder-ladder IMF is superior in performance (less hardware and less latency) compared to pipelined traditional IMF. The theoretical analysis is performed with metrics (critical path, number of resources, and maximum achievable frequency) to compare various architectures presented in this research work. © 2021 IEEE.