Browsing by Author "Gopala Swamy, B."

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    FPGA Accelerated Track to Track Association and Fusion for ADAS Distributed Sensors
    (Institute of Electrical and Electronics Engineers Inc., 2023) Gopala Swamy, B.; Reddy, G.H.; Srihari, P.; Shripathi Acharya, U.; Pardhasaradhi, B.
    The integration and amalgamation of sensor data in the automotive domain play a pivotal role in informing real-time decision-making for advanced driver assistance and safety (ADAS) systems. In a distributed architecture, the track-to-track association (T2TA) modules are responsible for associating the correct track pairs and subsequently fusion modules fuses the information. The T2TA and fusion modules operate within the CPU framework, often leading to elevated latency across the system. This paper introduces digital signal processing (DSP) architectures for the T2TA and fusion modules, designed to meet stringent constraints in terms of both area and latency. These modules encompass critical operations such as matrix inversion, vector-to-matrix multiplications, and matrix-to-matrix multiplications. The challenge of vector-to-matrix multiplications is effectively addressed through the utilization of the constant co-efficient multiplication technique. Additionally, matrix-to-matrix multiplication is performed by employing a vector-to-vector multiplication architecture with Block RAMs (BRAMs). Further-more, matrix inversion is realized through the LU decomposition method. Moreover, this paper presents an innovative approach to expedite the T2TA and fusion modules by harnessing folded DSP architecture within a system-on-chip (SOC) framework. The results of simulations substantiate that the proposed architectures exhibit a remarkable suitability for applications necessitating low area, low power consumption, and high throughput capabilities. © 2023 IEEE.
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    Systolic-Architecture-Based Matrix Multiplications and Its Realization for Multi-Sensor Bias Estimation Algorithms
    (Springer Science and Business Media Deutschland GmbH, 2021) Gopala Swamy, B.; Sripati Acharya, U.; Srihari, P.; Pardhasaradhi, B.
    The accelerators are gaining predominant attention in the HW/SW designs and embedded designs due to the less power consumption and parallel data processing capabilities compared to standard microprocessors and FPGA’s. In this paper, MSSKF (Multi-sensor Schmidt–Kalman filter)-based coupled bias estimation problem is considered for single target multiple sensors case. Here MSSKF augments the state vector and bias vector for bias estimation, results in computationally expensive as the dimensions of the state and sensors increases. Hence to address the computational complexity, digital signal processing (DSP) architectures are proposed and accelerated the algorithm to meet the real-time constraints. In the MSSKF algorithm, the overload of the algorithm is due to state covariance prediction and innovation covariance prediction. To realize the state covariance and innovation covariance, a folded DSP architecture and parallel processing based folded DSP architecture are proposed, respectively. The matrix multiplications are addressed with systolic arrays to gain the advantage of latency and parallel processing. Moreover, MSSKF using systolic array architectures simulated and synthesized in Vivado 2018.1 using Verilog and implemented on FPGA-Zynq-7000 board. The performance of the systolic-based accelerator realization was compared with normal matrix multiplication. © 2021, Springer Nature Singapore Pte Ltd.