Browsing by Author "Gagan, N."

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Design of a Fault-Tolerant Pseudo-3D Routing
(Institute of Electrical and Electronics Engineers Inc., 2023) Bhowmik, B.; Gagan, N.
A network on chip (NoC) exposes faults that disturb overall performance. Subsequently, a routing algorithm with fault tolerant facility has become a holistic aspect of reliable NoC communications. We propose a routing mechanism including fault tolerance in channels of a pseudo-3D mesh NoCs. The concept of a detour path is the foundation of the proposed solution. Its goal is to ensure the delivery of almost all packets with a detour of a few without utilizing broken or faulty communication functionalities. On evaluations, the suggested technique produces 11.47% greater throughput, 38.38% lesser latency, and 65.50% improved energy consumption compared to the baseline mesh NoC. Based on the findings, one may conclude that the proposed fault-Tolerant routing performs more effectively even at higher traffic load levels. Â© 2023 IEEE.
Long-Distance Communication via Pseudo-3D Networks-on-Chip
(Institute of Electrical and Electronics Engineers Inc., 2021) Gagan, N.; Bhowmik, B.
Conventional mesh-based interconnection architecture is simple to implement and verify. However, with the increase in nodes and network size, the architecture imposes high latency due to the lack of shorter paths between far nodes. This paper finds an alternative approach that improves performance for long-distance communication in a mesh NoC. The proposed method offers a variant of the 2D mesh topology named 'pseudo-3D mesh' in which a few new nodes are added in the upper layer of a 2D mesh NoC. Rigorous simulation results show that the proposed scheme provides acceptably high performance at the cost of little hardware overhead. Further, the proposed method improves the global and local packet latency by 19% and 24%, respectively, compared to a conventional 2D 7 Ã— 7 mesh NoC. Consequently, packet loss is improved by 50%, accelerating nearly 43% throughput gain and 47% energy consumption reduction. Â© 2021 IEEE.
TLM-NoC: Two Level Mesh Network-on-Chip for Performance Improvement
(Institute of Electrical and Electronics Engineers Inc., 2022) Gagan, N.; Bhowmik, B.
As the number of cores integrated into a system-on-chip (SoC) increases, the role played by this on-chip communication system becomes more and more critical due to communication bottleneck and scalability. The network-on-chip (NoC) design paradigm is today recognized as the most viable communication infrastructure over SoCs. However, the former architecture imposes latency concerns while the network size increases resulting in significant performance degradation. This paper finds an alternative solution for improving mesh NoCs, especially when long-distance communication takes place. The proposed solution suggests a variant of the 2D mesh topology named 'two-level mesh - network-on-chip (TLM-NoC)' in which a baseline mesh includes sparse mesh interconnection at the upper layer. The upper layer primarily establishes long-distance communications between nodes which in turn reduces latency and improves other metrics. Experimental results show adequate performance improvements by the TLM-NoC over traditional meshes. Evaluation of TLM-NoC shows latency improvement by 17.97%, resulting in 33.33% packet flit loss reduction and 26.80 % increased throughput. Further, the proposed architecture consumes 23.69% less energy for delivering traffic. Â© 2021 IEEE.
Topology Exploration for Long-Distance Communication
(Institute of Electrical and Electronics Engineers Inc., 2021) Gagan, N.; Bhowmik, B.
With the increase in the network size, the conventional network-on-chip (NoC) imposes high latency due to the lack of shorter paths between far nodes resulting in performance degradation. This paper proposes an alternative approach that improves performance for long-distance communication in a mesh NoC. The proposed method explores a new topology named 'pseudo-3D mesh' in which a few new nodes are added in the upper layer of a 2D mesh NoC. Experimental results show that the proposed scheme provides acceptably high performance at the cost of little hardware over-head. Â© 2021 IEEE.