Browsing by Author "Bhat, M.S."

Now showing 1 - 20 of 99

A 0.5V 300?W 50MS/s 180nm 6bit Flash ADC using inverter based comparators
(2012) Komar, R.; Bhat, M.S.; Laxminidhi, T.
This paper presents a 0.5 V, 50 MS/s, 6 bit Flash ADC designed using 180 nm CMOS technology. To reduce the silicon area and power requirement, an inverter based comparator is used in the design. Low threshold MOSFETs are used for the ultra low voltage operation. A simple clock delaying technique and back to back inverters in the comparator have been used to increase the power efficiency and speed of operation. A fat tree encoder design is used for digitizing comparator outputs. The measured SNDR at input frequency of 5.1 MHz is 31 dB. The measured maximum INL and DNL for a ramp input are 0.375 LSB and 0.025 LSB, respectively. The design consumes a very low power of 300 ?W. � 2012 Pillay Engineering College.
A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
(2013) Lad, K.; Bhat, M.S.
A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. � 2013 IEEE.
11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energyefficient successive approximation register ADC in 90 nm complementary metal-oxide- semiconductor
(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Laxminidhi, T.; Bhat, M.S.
In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample-and-hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energyefficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal-oxide-semiconductor process. The ADC core has a small area footprint of 0.00145 mm2 and has a figure-of-merit of 11.39 fJ/conv-step. © 2018, The Institution of Engineering and Technology.
14.5 fJ/conversion-step 9-bit 100-kS/s nonbinary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
(Institution of Engineering and Technology journals@theiet.org, 2018) Narasimaiah, J.D.; Bhat, M.S.
In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm2. At a 1 V supply and 100 kS/s, the ADC achieves a signal-to-noise and distortion ratio of 53.55 dB and consumes 0.47 ?W, resulting in a figure-of-merit of 14.5 fJ/conversion step. © The Institution of Engineering and Technology 2018.
A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC
(2012) Shrivastava, P.; Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.
This paper presents a low power 3.3 V, 500 kS/s 8bit successive approximation register ADC in 0.18?m technology. The DAC architecture employs charge recycling to produce 2-bits in one cycle i.e, it takes N/2 clock cycles to generate N-bits. The DAC architecture uses four rail to rail unity gain buffers and seven unit size capacitors in which one is half of the unit size to design ADC. Three comparators have been used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 56.64 kHz, is 48.14 dB and at 232.42 kHz is 47.03 dB. The simulated maximum INL as well as DNL is 0.5 LSB. The design consumes a low power of 1.8mW from the power supply of 3.3 V. � 2012 IEEE.
An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC
(2016) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.
This paper presents a low power 1V, 1.5MS/s 8-bit successive approximation register ADC in 90 nm technology. The DAC architecture employs fixed number of unit size capacitors and charge recycling through low power buffers to produce 2-bits in one cycle. The multiple reference voltage generation scheme in DAC, as demanded for 2 bits per cycle operation, is parasitic insensitive to a large extent. A two bit flash ADC is used to decide the 2-bits in each cycle. The simulated SNDR, at the input frequency of 17.7 kHz, is 49.2 dB and 48.44 dB at Nyquist frequency. The simulated DNL and INL are found to be within 0.9LSB and 0.5LSB respectively. The design consumes a power of 185 ?W from the power supply of 1V. � 2015 IEEE.
A 0.3-V, 2.4-nW, and 100-Hz fourth-order LPF for ECG signal processing
(John Wiley and Sons Ltd cs-journals@wiley.co.uk, 2020) Rao G, H.; Polineni, P.; Rekha, S.; Bhat, M.S.
An ultra-low voltage, low power bulk-driven voltage follower (VF) is proposed in this paper. Further, it is exploited to design a fourth-order low-pass filter (LPF) for electrocardiogram (ECG) signal processing. The filter is designed in UMC 180-nm CMOS technology and operates with an ultra-low supply voltage of 0.3 V. It consumes an extremely low power of 2.4 nW for a cutoff frequency of 100 Hz. Results of post-layout simulation show that the proposed filter provides a dynamic range (DR) of 51.6 dB even from a 0.3-V supply voltage. The filter achieves a Figure-of-merit (FoM) of 4.7 × 10?15, which is better than many designs listed in the literature. © 2020 John Wiley & Sons, Ltd.
A 0.3?V, 56?dB DR, 100?Hz fourth order low-pass filter for ECG acquisition system
(Elsevier Ltd, 2019) Polineni, S.; Hanumantha Rao, G.; Rekha, S.; Bhat, M.S.
This paper proposes an extremely low voltage, low power bulk-driven voltage follower (BD-VF). As an application of the proposed BD-VF, a 4th order low-pass filter (LPF) with cutoff frequency adjustable from 50 Hz to 250 Hz is designed for electrocardiogram (ECG) acquisition systems. The filter is implemented in UMC 180 nm CMOS technology occupying only 0.03 mm2 area. Post layout simulation results show that the filter offers 56 dB dynamic range even with an extremely low supply voltage of 0.3 V. The total power consumption of the filter is 4.8 nW for a cutoff frequency of 100 Hz. The Figure-of-merit (FoM) and capacitance/pole of the filter are 5.7 × 10?15 and 2.2 pF respectively. The proposed filter offers the lowest FoM compared to the state-of-the-art nW-class filters. © 2019 Elsevier Ltd
A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
(2013) Lad, K.; Bhat, M.S.
A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. Â© 2013 IEEE.
A 1.2V 1.3Î¼W Cascode Current Reuse Based Neural Amplifier with 113 dB Open-Loop Gain
(Institute of Electrical and Electronics Engineers Inc., 2023) Korada, S.; Bhat, M.S.
One of the major challenges in the acquisition of neural signals is the design of electronic signal acquisition system. Specialized amplifier circuitry is required in the neural recording system to accurately extract information from weak neural signals. High gain, high input impedance amplifiers are part of such systems. This paper presents the design of a high gain modified casocde current reuse open loop amplifier suitable for such applications. The amplifier has a open loop gain of 113 dB, a bandwidth of 10 kHz and unity-gain bandwidth (UGB) of 6.6 MHz. Further, design and simulation of high gain and low power neural amplifier is presented which uses the proposed high gain modified cascode current reuse amplifier with capacitive feedback. The neural amplifier has a closed loop gain of 45.8 dB over 85 Hz - 8.2 kHz and consumes approximately 1.3 Î¼W of power. The design and the simulation is done using the UMC 90nm CMOS process employing 1.2 V power supply. The small signal DC gain, bandwidth and power of the neural amplifier are found to be better than the previously published works. Â© 2023 IEEE.
A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique
(Springer Verlag, 2019) Polineni, S.; Bhat, M.S.; Rajan, A.
A fully differential energy-efficient switching scheme for binary-weighted capacitor digital-to-analog converter (DAC) is presented. It is observed that the proposed switching scheme reduces energy consumption of DAC by 97% and the capacitance area by 50% over the conventional ones. The effect of supply and common mode voltage variations on the linearity of successive approximation register (SAR) analog-to-digital converter (ADC) is reduced. Moreover, with this switching scheme, one can achieve the same dynamic range as the conventional one, with half the supply voltage as compared to the existing schemes. This makes the proposed switching method suitable for ultra-low-voltage SAR ADCs, which are widely used in biomedical applications. The proposed method is modelled using MATLAB. The results show that the nonlinearity (INL and DNL) caused by capacitor mismatch is reduced. The circuit-level implementation of 10-bit SAR ADC is simulated using UMC 90nm CMOS 1P9M process technology. © 2018, King Fahd University of Petroleum & Minerals.
A Compact 10-bit Nonbinary Weighted Switched Capacitor Integrator Based SAR ADC Architecture
(IEEE Computer Society help@computer.org, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.
A compact switched capacitor integrator (SCI) based successive approximation register (SAR) analog to digital converter (ADC) for data acquisition system is presented. This technique requires an operational transconductor amplifier (OTA), a comparator and four equal sized capacitors of moderate value for fully differential approach and the architecture is resolution independent. The reference voltage is generated by charge sharing between a reference capacitor and the input capacitor of a switched capacitor (SC) integrator. The DAC voltage for comparison is generated by accumulating the charges on the SC integrating capacitor. ADC being fully differential nature has wide input range and it is parasitic insensitive to a large extent. As a stand alone data converter it has small capacitance spread and hence its input capacitance is easy to drive. A 10 bit 0.9MHz sampling rate SAR ADC is designed using 180 nm CMOS technology, operating at 1.8 V supply, has effective number of bits (ENOB) of 9.5 at Nyquist frequency. The ADC occupies small die area compared to SAR with a binary weighted capacitor array. Â© 2019 IEEE.
A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture
(Springer, 2019) Bhat, K.G.; Laxminidhi, T.; Bhat, M.S.
A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 ?W achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 16× degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits. © 2019, Indian Academy of Sciences.
A fourth-order Partial Differential Equation model for multiplicative noise removal in images
(IEEE Computer Society, 2013) Bini, A.A.; Bhat, M.S.
In coherent imaging, the sensed images are usually corrupted with multiplicative data dependent noise. Unlike additive noise, the presence of multiplicative noise destroys the information content in the original image to a great extent. In this paper, we propose a new fourth-order Partial Differential Equation (PDE) model with a noise adaptive fidelity term for multiplicative Gamma noise removal under the variational Regularization framework. Variational approaches for multiplicative noise removal generally consist of a maximum a posteriori (MAP) based fidelity term and a Total-Variation (TV) regularization term. However, the second-order TV diffusion approximates the observed images with piecewise constant images, leading to the so-called block effect. The proposed model removes the multiplicative noise effectively and approximates observed images with planar ones making the restored images more natural compared to the second-order diffusion models. The proposed method is compared with the recent state-of-the art methods and the effective restoration capability of the filter is demonstrated experimentally. Â© 2013 IEEE.
A fully differential switched-capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications
(John Wiley and Sons Inc, 2021) Polineni, S.; Rekha, S.; Bhat, M.S.
A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 ?W across target resolutions (8–15 bits). © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology.
A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications
(Institute of Electrical and Electronics Engineers Inc., 2014) Jagadish, D.N.; Bhat, M.S.
A low voltage and low power inverter based differential amplifier is presented. The input stage is fully differential in operation and the output stage employ class C inverter to enhance the gain. An on-chip body bias improves the slew rate performance. The amplifier is implemented in UMC 90 nm technology. With load capacitance of 100fF, the amplifier delivers DC gain of 81dB and unity gain bandwidth of 33.88MHz at 41Â° phase margin. For a dual power supply voltage of Â±350mV, the quiescent current and power consumption are 2.37Î¼A and 1.66Î¼W respectively. The amplifier achieves a figure of merit of 2117. With the bulk of all the transistors slightly forward biased by a fixed bias potential, the power dissipation of 672nW and figure of merit of 5431 are achieved. Â© 2014 IEEE.
A low-energy area-efficient dual channel SAR ADC using common capacitor array technique
(Institute of Electrical and Electronics Engineers Inc., 2016) Reddy, N.S.; Jagadish, D.N.; Bhat, M.S.
A novel low energy and area efficient Dual-Channel Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is presented. To achieve area efficiency, a common Capacitor Array (CA) technique is proposed wherein we use only N+1 CAs instead of 2N for N-channels in a differential architecture. In the present design we use three CAs instead of four for two channels. This reduction in CA count not only reduces the capacitance area but also the total energy required to charge and discharge the CAs. A 7-bit dual channel SAR ADC using the proposed technique is implemented in UMC 0.18Î¼m CMOS technology. At a sampling rate of 4 MS/s and a supply voltage of 1.8 V, each channel consumes 43.85 Î¼W and exhibits a FOM of 101.14 fJ/conversion step. Â© 2016 IEEE.
A nonlinear level set model for image deblurring and denoising
(Springer Verlag service@springer.de, 2014) Bini, A.A.; Bhat, M.S.
Image deblurring and denoising are fundamental problems in the field of image processing with numerous applications. This paper presents a new nonlinear Partial Differential Equation (PDE) model based on curve evolution via level sets, for recovering images from their blurry and noisy observations. The proposed method integrates an image deconvolution process and a curve evolution based regularizing process to form a reaction-diffusion PDE. The regularization term in the proposed PDE is a combination of a diffusive image smoothing term and a reactive image enhancement term. The diffusive and reactive terms present in the model lead to effective suppression of noise with sharp restoration of image features. We present several numerical results for image restoration, with synthetic and real degradations and compare it to other state-of-the-art image restoration techniques. The experiments confirm the favorable performance of our method, both visually and in terms of Improvement in Signal-to-Noise-Ratio (ISNR) and Pratt's Figure Of Merit (FOM). © 2013 Springer-Verlag Berlin Heidelberg.
A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry
(Institute of Electrical and Electronics Engineers Inc., 2017) Sharma, B.S.; Bhat, M.S.
Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using In0.75 Ga0.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent Ion/Ioff. Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of In0.75 Ga0.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm-max â‰ˆ 293.626 Î¼S/Î¼m, subthreshold slope SS â‰ˆ 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V. Â© 2017 IEEE.
A Scheme for efficient and equitable use of public utilities through supervisory and distributed control
(Institute of Electrical and Electronics Engineers Inc., 2018) Shreenivasa, K.; Bhat, M.S.; Rekha, S.
Clean water and electricity are the two major public utilities for any society and it is the responsibility of each consumer to use these resources efficiently and minimize the wastage. This paper presents a distributed control scheme to address these issues for each utility. In this scheme, wireless sensor network is used for on-line monitoring and automated control of water in overhead tanks. In a similar way, using energy meters and intelligent circuit breakers, the power consumption is remotely monitored and power delivery is automated. A cloud based user application is developed through which authorized operators can view the complete data of water flow as well as energy consumption at desired locations on a single graphical user interface (GUI). The distributed control is developed using Internet enabled embedded boards along with sensors and supporting network nodes. IBM's Watson IoT platform is used for data acquisition, analysis and control. Â© 2018 IEEE.