Browsing by Author "Bhat, M. S."

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Design of Low Power Successive Approximation Register Analog-To-Digital Converter
(National Institute of Technology Karnataka, Surathkal, 2017) D. N, Jagadish; Bhat, M. S.
Battery operated electronic devices are severely constrained by power dissipation and voltage. Portable devices, in particular, medical implants and wireless sensors insist on smaller die size. Analog-to-digital converter (ADC) interfaces the real analog signal to the digital domain. Being the key component in these integrated circuits, ADC’s design has to meet the said constraints. This thesis addresses the design challenges, strategies and circuit techniques of ultra-low-power and area efficient SAR ADCs. In the said applications, since the conversion speed requirements are in the range of few Hz to MHz, a successive approximation register (SAR) ADC seems to be most appropriate. SAR ADCs are usually implemented using binary weighted capacitors. The ADC at medium-to-high resolution is limited by capacitor mismatch, which eventually is the bottleneck. The size of a capacitor array in itself is an indicator of power and area performance of the SAR ADC. As a first step towards minimizing power dissipation, capacitor matching is improved by having nonbinary weighted capacitors. Second, efforts are made to remove the dependency of power dissipation on capacitor array. Third, parasitics and thermal noise affecting conversion accuracy are suitably addressed. The said strategies are infused in the proposed two novel SAR ADC architectures. To demonstrate the efficacy, a 9 bit 100 kS/s 1 V dual capacitor array SAR ADC and an 8 bit 780 kS/s ±0.35 V switched capacitor based SAR ADC are implemented in CMOS 90 nm technology node. The performances are verified through simulation of layout extracted netlist. Respective figure-of-merit and core area of the implemented dual capacitor array SAR ADC are 14.5 fJ/c-s and 0.00371 mm2. The same, for the case of switched capacitor based SAR ADC are 11.39 fJ/c-s and 0.00145 mm2. Further, the switched capacitor based SAR ADC gels well into ∆Σ modulator loop and its usefulness in noise shaping is verified by simulation of the modelled ADC.
Performance and Reliability Codesign of Drain Extended MOS Devices for Advanced SoC Applications
(National Institute of Technology Karnataka, Surathkal, 2018) Somayaji B., Jhnanesh; Bhat, M. S.
In order to address the demands of advanced functionalities of System on Chips (SoC), interfacing various modules operating at different voltage levels is very much essential. In this work, effectively utilizing the superjunction concept with Drain extended MOS (DeMOS) device is explored for SoC applications. For the first time, design of four different CMOScompatible DeMOS devices, namely, Double and Triple RESURF (Single Superjunction (SJ) devices) and Multiple RESURF (Multiple SuperjunctionsI and II) devices is studied for optimized breakdown voltage and onresistance parameters. The work investigates the primary parameters of the devices relating to p-implant. The device parameters are optimized to maximize the breakdown voltage (VBD) to on-resistance (RON) ratio. The superjunction concept has helped in improving the breakdown voltage by 2× without affecting the on-resistance or has allowed reducing on-resistance by 2.5× without changing the breakdown voltage. Also, hot carrier generation, safe operating area concerns and electrostatic discharge (ESD) reliability behavior is studied for various superjunction DeMOS structures and is compared with conventional DeMOS device. Further, the work is extended to tri-gate structures. Four different Drain extended FinFET devices are proposed, namely, Silicon On Insulator based, p-stop based, well doped with and without p-implant structures. The devices are designed and simulated to explore the suitability of DeFinFETs for submicron high voltage applications. The well doped DeFinFET devices give the best performance metrics compared to SOI and p-stop based DeFinFETs.
RF Mems Capacitive Switches for Tunable Microsystems
(National Institute of Technology Karnataka, Surathkal, 2019) Shajahan. E. S.; Bhat, M. S.
This thesis deals with the design, simulation, fabrication and characterization of low voltage Radio Frequency Micro-electro-mechanical Systems (RF MEMS) capacitive shunt switches. Switch membrane geometry is modified to achieve low actuation voltage in the range of 10 − 18:5 V and good RF performance in different bands. Commercial CAD tool CoventorWare is used for design and DC analysis while RF analysis is carried out using ANSYS HFSS and Agilent ADS. Inductive tuning of switch membranes is employed to tune the RF characteristics to optimize X, Ku, K and Ka band performance. Inductance is added to the shunt membranes by modifying beam geometry. The fabrication of the switches is carried out as a five mask surface micromachining process on silicon substrate. DC and RF parameters are measured and are found to be very good. Further, the design, electromechanical and electromagnetic modeling of Single Pole Four Throw switch is carried-out as part of the thesis. The DC and RF simulation results show low actuation voltage of 13.75 V, insertion loss and isolation better than 0.7 dB and 52 dB respectively in X-band. Additionally, wide-band and narrow-band tunable bandpass filters in X and Ku bands are designed on co-planar waveguides using cantilever series and capacitive shunt switches and realized as cascaded sections of highpass and lowpass filters. Tunability in center frequency from 11.76 GHz to 15.86 GHz is achieved by the controlled actuation of shunt switches and bandwidth tunability from 2.34 GHz to 5.4 GHz by series switches. Further, distributed true time delay phase shifter is designed on slow wave co-planar waveguide employing five sets of metallic membranes as floating shield. The controlled actuation of the floating membranes result in variable capacitive loading and thereby achieving good phase tunability. The design provided a phase shift tunability in the range 18◦ to 28◦ at 10 GHz, 124◦ to 180◦ at 70 GHz and a liniar variation in the above range for the intermediate frequencies.