Mehra, H.Bhat, M.S.2020-03-302020-03-3020192018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings, 2019, Vol., , pp.163-168https://idr.nitk.ac.in/handle/123456789/8193Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction is all the more important to derive maximum performance mileage. Retiming is a powerful sequential optimization technique used to move registers across the combinational logic or to optimize the number of registers to improve performance via power-delay trade-off, without changing the input-output behavior of the circuit. This paper presents a high-level technique to retime a given sequential circuit to achieve lower clock period and a lower register count and their trade-off. The techniques used in this paper include cutset retiming, retiming for clock period minimization and retiming for register minimization. An environment is created using MATLAB, which takes a non-retimed circuit in the form of a netlist and a retimed netlist is generated with reduced critical path and/or with reduced number of flip-flops, thereby improving the overall performance. � 2018 IEEE.Book chapter