Polineni S.Bhat M.S.Rekha S.2021-05-052021-05-052020Circuits, Systems, and Signal Processing , Vol. 39 , 11 , p. 5352 - 5370https://doi.org/10.1007/s00034-020-01437-3https://idr.nitk.ac.in/handle/123456789/16403In this work, a switched capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) using a passive reference charge sharing and charge accumulation is proposed. For N-bit resolution, the fully differential version of this architecture needs only 6 capacitors, which is a significant improvement over conventional binary-weighted SAR ADC. The proposed SAR ADC is first modeled in MATLAB, and the effect of practical operational transconductance amplifier limitations such as finite values of gain, unity-gain bandwidth and slew rate on ADC characteristics is verified through behavioral simulations. To validate the proposed ADC performance, an 11-bit 2 kS/s SAR ADC is designed and laid out in UMC 180 nm 1P6M CMOS technology with a supply voltage of 1.8 V. The total design occupies an area of 568μm×298μm and consumes a power as less as 0.28μW. It is found that the integral nonlinearity and differential nonlinearity of this ADC are in the range + 0.35/− 0.84 least significant bit (LSB) and + 0.1/− 0.6 LSB, respectively. In addition, dynamic performance test shows that the proposed SAR ADC offers an effective number of bits of 10.14 and a Walden figure of merit (FoMW) of 0.12 pJ/conv-step. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.Article