Hegde, K.V.Kulkarni, V.Harshavardhan, R.Sumam David, S.2026-02-062015Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015, 2015, Vol., , p. 196-201https://doi.org/10.1109/IPDPSW.2015.126https://idr.nitk.ac.in/handle/123456789/32297In this paper, we propose an adaptive reconfigurable architecture for image denoising. First part of this paper outlines an efficient noise detection hardware for Gaussian & impulse noise detection and suitable filters for denoising. With a robust noise detection method including a novel Gaussian noise detection method, we also explore the dynamic detection of noise in an image giving adaptability to the architecture for a better quality of denoising. Proposed architecture includes a decision making unit to find out the presence of noise as well as type of the noise, based on which a suitable filter is employed during run-time. An onboard microprocessor controls the reconfiguration and dataflow. Proposed architecture is tested on Xilinx Virtex-6 FPGA with localized noise and mixed noise conditions and it gives superior performance compared to the standard filters used. High quality denoising is achieved with simple filters on a reconfigurable region utilizing smaller area and lesser hardware resources. © 2015 IEEE.adaptive architecturesdynamic reconfigurationFPGAsimage denoisingimage processing